Ciaran Feeney

This letter demonstrates an on-silicon integrated thin film coupled inductor using a novel cascade matrix concept to suit multiphase integrated voltage regulator (IVR) applications. The novel cascade matrix coupled (CMC) stripline inductor facilitates all-phase-coupled configuration to reduce the phase ripple current in IVRs. It also shows excellent scalability and neat floor planning. Moreover, the proposed CMC inductor uses double layer metal scheme for windings and interconnects, which significantly reduces the ac winding resistance. A four-phase CMC inductor has been successfully fabricated on-silicon substrate and characterized, which uses conventional thin film magnetic core deposition process to achieve in-plane magnetic uniaxial anisotropy. The device occupies 3.2 × 1.7 mm ² floor area and provides 19.5 nH phase inductance with 120 mΩ dc resistance. The saturation current for each phase is up to 0.4 A when the phase inductance drops by approximately 20%. The coupling coefficient between any two phases of the proposed CMC inductor is 0.27, much higher and more controllable than that of toroid core-based coupled inductors.

Coupled inductors offer significant advantages over their uncoupled counterparts; however, with these advantages come a number of additional design caveats. The factors affecting the design and optimization of coupled stripline microinductors for PwrSoC applications are outlined, which include device area, the number of coupled phases, duty cycle, paralleling of coupled inductors, switching frequency, as well as thermal and saturation constraints. Results of this analysis are presented and discussed along with guidelines for the design of coupled stripline microinductors, which show that paralleling coupled inductors is the best route toward higher output current. Analytical models predict a peak inductor efficiency of 86.8% and 86.3% for fabricated 3 and 5-phase coupled stripline microinductors with an Ni ₄₅ Fe ₅₅ core, respectively. Models are verified by measurements on prototype 3 and 5-phase converters with parallel coupled stripline microinductors over a range of operating conditions.

In this paper, models that account for the duty cycle and phase shift angle of the applied phase voltages in coupled stripline microinductors are presented and are shown to have a significant impact on harmonic current amplitudes and therefore microinductor efficiency. The impact of a high coupling factor between two windings surrounded by a single core is also investigated. The models are validated using finite-element analysis and measurements. A three-phase-coupled microinductor has been fabricated with a Ni ₄₅ Fe ₅₅ core and analyzed for a number of operating conditions. A prototype 1.6 W, three-phase converter utilizing this inductor has also been measured and is discussed in detail. The coupled microinductor is predicted to have a peak efficiency of 86.6% at 20 MHz in the prototype circuit.

Inductor-on-silicon research to date has focused on optimizing technologies for maximum power density and efficiency, with most design procedures based on computationally intensive methods. In this paper, a simple and intuitive method for designing microinductors based on a given dc–dc converter specification, which includes accurate models for all loss components, is presented. A detailed examination of variations in designs to realise the same circuit performance is presented. Finally, finite element analysis simulations demonstrating the accuracy of the models are given, along with measured results.

The purpose of this paper is to show that distributing microinductors in parallel can reduce light-load losses, while also maintaining the same overall footprint area and the same effective inductance as a single microinductor. The performance of parallel microinductors is compared in a number of configurations to demonstrate which configuration provides the best overall performance in terms of circuit size, conversion efficiency, and power handling. Light-load saving techniques are implemented demonstrating the potential of parallel inductors to improve efficiency at light-load. Measured and modeled results of efficiency versus load are presented for the prototype DC-DC converters explored, and a peak efficiency of 74% is predicted for a 1.8 W, 20-MHz DC-DC converter including microinductors.