Min-Woong Seo

This article presents a 3-Mpixel (Mp) three-stacked digital pixel sensor (DPS) featuring the world’s smallest pixel pitch of $2.988~\mu $ m, achieving a low temporal random noise (RN) of 1.16 e-rms and a high dynamic range (HDR) of 123 dB in global-shutter (GS) operation mode for versatile applications. To realize both the low RN and HDR performance, the developed DPS employs a pixel-parallel analog-to-digital converter (P-ADC) architecture with an extremely narrow noise bandwidth (BW), as well as a split photodiode (PD) structure combined with signal chopping operation to mitigate the LED flicker phenomenon. In addition, the DPS leverages a three-stacked sensor architecture, which enables a compact pixel footprint while enhancing on-chip image signal processing (ISP) capabilities and supporting efficient HDR merging. Chip-level evaluations confirm the superior performance of the proposed DPS, demonstrating its potential for high-performance imaging in mobile, automotive, machine vision (MV), and other advanced applications.

This article presents a low random noise, a low-power, and a high-speed 2-mega pixels (Mp) global-shutter (GS)-type CMOS image sensor (CIS) using an advanced dynamic random access memory (DRAM) technology. GS CIS is one of the alternatives to solve image distortion issues caused by a conventional rolling-shutter (RS) CIS operation, since a 2-D image data can be simultaneously sampled by the in-pixel analog memory. To achieve a high-performance GS CIS, we proposed a novel architecture for digital pixel sensor (DPS) which is a high-speed GS operation CIS with a pixel-wise analog-to-digital converter (ADC) and an in-pixel digital memory. The major technologies of the proposed DPS can be summarized as follows: 1) two large coupling capacitors with mature DRAM technology; 2) extremely narrow pitch Cu-to-Cu (C2C) bond; and 3) finally low-powered ADC with a near sub-threshold operation. A perfect auto-zero operation for ADC is implemented using two DRAM capacitors, and a large number of transistors have to be integrated in the single pixel for realizing pixel-level ADC. Thus, each pixel has two fine-pitch C2C interconnections. This makes it possible to realize wafer-level stacked unit pixel. The proposed DPS with low-power consuming analog circuits has been successfully designed and developed for extremely fast-readout speed of max. 1200 frames per second (fps) and high sensitivity for low-illumination conditions.

This paper presents a time-resolved (TR) CMOS image sensor (CIS) using two-tap near-infrared (NIR) lock-in pixels with background light (BGL) cancelling capability for remote heart rate (HR) detection. Aimed to the application, the sensor features a 1024 (V) x 1280 (H) spatial resolution with 412 (V)x 1280 (H) region-of-interest-readout (ROI-readout) at 30 fps, a high sensitivity of 134.8 ke⁻/lux · s, and an ultra-low temporal random noise of 1.13 erms⁻ at analog gain of 64. A maximum charge modulation ratio of 90.1% is obtained for realizing lock-in operation by means of in-pixel lateral electric field charge modulator (LEFM). The remote HR detection is achieved by capturing the heart-beat-induced temporal variation of the oxy-hemoglobin (HbO₂) concentration by the developed TR CIS with NIR lock-in technique, and larger than 98% detection accuracies are attained under both non-visible-light condition and fluctuant brightness ambient-light environments. This remarkable feature demonstrates the superiority of the proposed method for driver monitoring applications in particular.

A programmable sub-nanosecond time-gated four-tap CMOS lock-in pixel (LIP) image sensor that uses an in-pixel pulse generator (PG) is developed for time-resolved (TR) biomedical imaging applications, such as a fluorescence lifetime imaging microscopy (FLIM). We demonstrate the system's effectiveness with simulations and measurements. Using pixel-level PG circuits, very narrow time windows (TWs) that are less than 0.8 ns can be used for charge modulation. This rapid gating allows very weak signals from living cells to be captured with a high signal-to-noise ratio (SNR). The prototype CMOS imaging system displays a fast intrinsic response of 170 ps at 472 nm and a very low temporal random noise of 0.85 e-rms at 45 frames/s under truly correlated-double-sampling operation using two-stage charge transfer. Four outputs from the LIPs allow real-time fluorescence lifetimes (FLTs) measurement, even from samples with multiple FLT components.

In the past several years, CMOS image sensors (CISs) with sub-single-electron noise level, particularly, deep sub-electron read noise (less than 0.5e-rms), have been reported. Such an ultra-low noise level is realized with a reduced floating diffusion (FD) node capacitance for attaining the high pixel conversion gain (CG) [1,2], and a high-gain readout circuitry with noise-reduction capabilities [3,4]. Recently, a reset-gate-less (RGL) CMOS image sensor has been reported [5]. It shows an excellent read noise performance using an optimized pixel structure for high CG and high-gain column ADC with multiple sampling. In this technique, however, a very high pulsed voltage of approximately 25V for the FD reset is essential to cause a punch-through effect. It is not suitable for image sensors with high pixel resolution and high-speed signal readout.