Hoyoung Yoo

Global Navigation Satellite Systems (GNSSs) provide essential position, velocity, and time (PVT) information worldwide. Accurate evaluation of GNSS signals and receiver performance requires realistic simulation environments, particularly for the carrier-to-noise-density ratio (C/N₀), a critical indicator reflecting signal quality dependent on satellite elevation angles. This paper presents the development of a GNSS testbed specifically designed to simulate and estimate C/N₀ values, focusing on GPS L1 C/A signals. The proposed testbed comprises three main components, a satellite simulator that controls signal power accurately according to satellite elevation angles, an up-/down-converter for RF/IF band conversion, and a signal receiver that estimates C/N₀ using the Narrowband–Wideband Power Ratio (NWPR) method. The performance of the proposed testbed was evaluated under four scenarios, namely static, dynamic, jamming, and real-signal. In the static scenario, the proposed system achieved a maximum C/N₀ estimation RMSE of 0.60 dB-Hz for satellites with elevation angles above 30° and 1.63 dB-Hz for those below 30°. In the dynamic scenario, the corresponding RMSE values were 0.68 dB-Hz and 0.86 dB-Hz, whereas under jamming conditions they increased to 2.08 dB-Hz and 2.12 dB-Hz, respectively. Furthermore, in the real-signal scenario, the C/N₀ values estimated by the proposed testbed exhibited trends consistent with those reported by a commercial u-blox receiver processing the same live-sky signals, thereby confirming its reliability under actual GNSS reception conditions. These results demonstrate that the proposed GNSS testbed enables reliable C/N₀ simulation and estimation for GNSS receiver performance evaluation.

This paper presents the efficient digital Ex-core Neutron Flux Monitoring System (ENFMS) based on Field Programmable Gate Array (FPGA), designed to precisely measure reactor power levels across a wide operational range from 10⁻⁸ % to 10² %. Conventional analog based ENFMS inherently suffers from low system performance, complex maintenance, susceptibility to environmental noise, and issues related to chip obsolescence. To address these challenges, the proposed system employs FPGA based digital signal processing, implementing three optimized measurement modes, namely Pulse, Mean Square Value (MSV), and Current, to effectively cover the entire operational range. A linear interpolation algorithm also provides smooth and continuous transitions between overlapping modes. Furthermore, the System on Chip (SoC) architecture integrates all signal processing functions onto a single FPGA chip, significantly reducing system size, complexity, and power consumption. Experimental evaluations performed on a Xilinx Kintex UltraScale FPGA platform demonstrated a short latency of approximately 3.49 μs at a 500 MHz clock frequency, high data throughput of 8.0 GB/s, and power consumption of about 6.3 W. Moreover, the system exhibited excellent measurement accuracy with a low RMS error of 0.0197 V throughout the entire operational range. Consequently, the proposed digital ENFMS significantly improves potential applicability, accuracy, and maintainability, making it well suited not only for existing nuclear instrumentation systems but also for emerging reactor technologies such as Small Modular Reactors (SMRs).

This paper introduces an innovative Interpolation-based Radar Simulation System (IRSS) designed to simulate Doppler frequencies across multiple frequencies with minimal hardware complexity. Traditional radar simulation systems, such as Analog Radar System Simulators (ARSS) and Digital Radar System Simulators (DRSS), face challenges when supporting multi-frequency simulations due to the need for parallel processing of individual Doppler frequencies. The proposed IRSS exploits linear interpolation and superposition property, enabling a single interpolation process to handle multiple frequency components efficiently. The IRSS structure was implemented using an FPGA-based USRP, and its performance was evaluated through experim-ental testing. The results demonstrated that the IRSS accurately generated Doppler frequencies for both single and multi-frequency signals, maintaining consistency with theoretical predictions. The system effectively simulated Doppler shifts for various target speeds while preserving hardware simplicity, unlike traditional simulators that require increased resources proportional to the number of frequencies. This research highlights the advantages of using linear interpolation to reduce hardware complexity and improve scalability in radar simulators. Consequently, the proposed IRSS provides a cost-effective and efficient solution for modern radar systems that demand multi-frequency capabilities, making it well-suited for applications in complex environments such as autonomous vehicles, military operations, and aviation.

Fully Homomorphic Encryption (FHE) allows computations on encrypted data without decryption, providing strong security for sensitive information. However, computational and memory demands for FHE are significant challenges, particularly in the Number Theoretic Transform (NTT) phase. This paper presents three efficient Twiddle Factor Generators (TFGs) to address these challenges: the Half-Memory TFG, the On-the-fly Serial TFG, and the On-the-fly Parallel TFG. The Half-Memory TFG reduces memory usage by storing only half of the twiddle factors and calculating the rest as needed. The On-the-fly Serial TFG eliminates memory requirements by computing twiddle factors, while the On-the-fly Parallel TFG enhances computational speed through parallel processing. Implemented on the FPGA KCU105 board, these TFGs demonstrated significant improvements in hardware resource utilization and computational efficiency. The Half-Memory TFG effectively reduces memory footprint, the On-the-fly Serial TFG eliminates memory usage with acceptable computational overhead, and the On-the-fly Parallel TFG offers superior performance for high-throughput applications. These innovations make FHE more practical for real-world applications, contributing to the broader goal of enabling secure, privacy-preserving computations on encrypted data.

A lot of research on deep learning and big data has led to efficient methods for processing large volumes of data and research on conserving computing resources. Particularly in domains like the IoT (Internet of Things), where the computing power is constrained, efficiently processing large volumes of data to conserve resources is crucial. The processing-in-memory (PIM) architecture was introduced as a method for efficient large-scale data processing. However, PIM focuses on changes within the memory itself rather than addressing the needs of low-cost solutions such as the IoT. This paper proposes a new approach using the PIM architecture to overcome memory bottlenecks effectively in domains with computing performance constraints. We adopt the RISC-V instruction set architecture for our proposed PIM system’s design, implementation, and comprehensive performance evaluation. Our proposal expects to efficiently utilize low-spec systems like the IoT by minimizing core modifications and introducing PIM instructions at the ISA level to enable solutions that leverage PIM capabilities. We evaluate the performance of our proposed architecture by comparing it with existing structures using convolution operations, the fundamental unit of deep-learning and big data computations. The experimental results show our proposed structure achieves a 34.4% improvement in processing speed and 18% improvement in power consumption compared to conventional von Neumann-based architectures. This substantiates its effectiveness at the application level, extending to fields such as deep learning and big data.

Data acquisition systems that receive analog signals, convert them to digital, and perform signal processing are used in a variety of systems that use acoustics, radar, sonar, indoor localization, and navigation. The previous systems, such as NI USRP-RIO, are expensive to build, and the number of signals a single device can receive is limited to between two and four. In order to receive more channels of signals, multi-channel data acquisition systems using ADCs operating at tens of MSPS have been proposed. However, these systems require additional processing time because data acquisition and signal processing are performed on different devices. In this paper, we propose a multi-channel data acquisition system using a 16-channel ADC that can support up to 100 MSPS. In particular, to reduce unnecessary signal transmission time, we propose a one-chip structure where all processes are performed on a single chip. Also, we propose a data acquisition system that applies pipelining techniques to enable real-time processing. To verify the proposed system, we used TI ADS52J90 and a Kintex UltraScale KCU105 evaluation board, and confirmed that it is possible to receive and process all channels simultaneously. Furthermore, it is possible to configure a real-time system by adjusting the speed of the signal-processing operation and the speed of the communication interface. Therefore, the proposed system is expected to reduce the cost of system construction by performing signal reception and processing with a single chip, and to reduce the time required for overall signal processing.

The rapid advancement in AI requires efficient accelerators for training on edge devices, which often face challenges related to the high hardware costs of floating-point arithmetic operations. To tackle these problems, efficient floating-point formats inspired by block floating-point (BFP), such as Microsoft Floating Point (MSFP) and FlexBlock (FB), are emerging. However, they have limited dynamic range and precision for the smaller magnitude values within a block due to the shared exponent. This limits the BFP’s ability to train deep neural networks (DNNs) with diverse datasets. This paper introduces the hybrid precision (HPFP) selection algorithms, designed to systematically reduce precision and implement hybrid precision strategies, thereby balancing layer-wise arithmetic operations and data path precision to address the shortcomings of traditional floating-point formats. Reducing the data bit width with HPFP allows more read/write operations from memory per cycle, thereby decreasing off-chip data access and the size of on-chip memories. Unlike traditional reduced precision formats that use BFP for calculating partial sums and accumulating those partial sums in 32-bit Floating Point (FP32), HPFP leads to significant hardware savings by performing all multiply and accumulate operations in reduced floating-point format. For evaluation, two training accelerators for the YOLOv2-Tiny model were developed, employing distinct mixed precision strategies, and their performance was benchmarked against an accelerator utilizing a conventional brain floating point of 16 bits (Bfloat16). The HPFP selection, employing 10 bits for the data path of all layers and for the arithmetic of layers requiring low precision, along with 12 bits for layers requiring higher precision, results in a 49.4% reduction in energy consumption and a 37.5% decrease in memory access. This is achieved with only a marginal mean Average Precision (mAP) degradation of 0.8% when compared to an accelerator based on Bfloat16. This comparison demonstrates that the proposed accelerator based on HPFP can be an efficient approach to designing compact and low-power accelerators without sacrificing accuracy.