Aniruddha Kanhe

Early-stage breast cancer diagnosis requires biosensors that are not only highly sensitive but also energy efficient and capable of detecting ultra-low HER2 (C-erbB-2) biomarker concentrations in saliva and serum, enabling reliable early-stage screening. Since biosensor sensitivity strongly depends on the subthreshold behaviour of the sensing transistor, Tunnel Field Effect Transistors (TFETs) are attractive due to their inherently steep switching enabled by band-to-band tunneling. While gate engineering through double-gate (DG) and triple-gate (TG) architectures improves electrostatic control and source heterojunction (HJ) engineering enhances tunneling efficiency, their combined impact on practical biosensing performance must be evaluated across a broader figure-of-merit space beyond sensitivity alone. To address this, a comparative simulation study of gate-engineered DG-TFET, TG-TFET, and gate- and source-engineered HJ-TG-TFET biosensors was carried out for C-erbB-2 detection in clinically relevant saliva and serum concentration ranges. The devices are evaluated using a broad biosensor performance framework, including sensitivity, power dissipation, limit of detection, detection margin, steric-hindrance tolerance, and signal-to-noise ratio. The results show that while gate engineering improves sensitivity, the combined gate- and source-engineered HJ-TG-TFET proposed in this work achieves the best overall trade-off, simultaneously delivering better sensitivity, lower power dissipation, superior low-concentration detectability for early-stage diagnosis, improved detection margin, and stronger robustness against steric hindrance. These findings establish HJ-TG-TFET as a promising energy-efficient biosensor for early-stage C-erbB-2 breast cancer biomarker detection and demonstrate that combined gate and source engineering is a highly effective pathway to improve practical TFET biosensor performance.

Approximate computing plays a vital role in accelerating large-scale data processing for error-resilient applications. Approximate adders are designed to trade off computational accuracy for reduced delay and lower hardware complexity, making them well-suited for such domains. This paper presents a novel approximate adder integrated into single-precision floatingpoint adder for mantissa addition. The proposed adder employs a carry prediction logic to improve the accuracy without increasing hardware cost. Implemented in SCL 180nm CMOS technology, the proposed design achieves average improvements of 50.56% in standard deviation, 59.66% in mean absolute error, 56.13% in normalized mean error distance, and 81.40% in mean square error compared to existing approximate adders. It further demonstrates 10.16% in delay, 12.7% lower power consumption and 45.5% fewer gates than an accurate reference adder. With a 6.68% carry prediction error rate, the architecture delivers balanced accuracy-speed-efficiency trade-offs, making it promising for high-speed, low-power VLSI applications like signal processing and machine learning accelerators.

‘Frame blocking’ or ‘Framing’ is a technique that divides a time-sampled speech or audio signal into consecutive and equi-sized short-time frames, either overlapped or non-overlapped, for analysis. The framing hardware architectures (FHA) in the literature support framing speech or audio samples of specific word size with specific frame size and frame overlap size. However, speech and audio applications often require framing signal samples of varied word sizes with varied frame sizes and frame overlap sizes. Therefore, the existing FHAs must be redesigned appropriately to keep up with the variability in word size, frame size and frame overlap size, as demanded across multiple applications. Redesigning the existing FHAs for each specific application is laborious, prompting the need for a configurable intellectual property (IP) core. The existing FHAs are inappropriate for creating configurable IP cores as they lack adaptability to accommodate variability in frame size and frame overlap size. Therefore, to address these issues, a novel FHA, adaptable to accommodate the desired variability, is proposed. Furthermore, the proposed FHA is transformed into a field-programmable gate array-based soft, ready-to-use and configurable frame blocking IP core using the Xilinx^® Vivado^™ tool. The resulting IP core is versatile, offering configurability for framing in numerous applications incorporating real-time digital speech and audio systems. This research article discusses the proposed FHA and frame blocking IP core in detail.