Said Ben Alla

Vibration monitoring increasingly classifies on the sensing node. We ask where the cost of running and securely updating a small classifier on an FPGA system-on-chip node lies. One Q4.12 multilayer perceptron for bearing-fault detection, trained on 40 CWRU recordings over four loads and three severities, is deployed bit-exactly on an ESP32-S3, a Cortex-A53 and a custom AXI4-Lite accelerator of the same Zynq UltraScale+ device (Kria KV260), checked on all 2132 windows. The fabric computes one inference in 36 cycles (0.36 µs), yet the latency under the PYNQ driver is 133.2 µs; a native-C driver reduces it to 3.59 µs, placing 95–97% of the per-transaction cost in the host software stack. Moving the update decision into the fabric, with the ASCON-AEAD128 tag check, version freshness and staging enforced in hardware, rejects every tested forgery, replay and direct write, and cuts a 608-byte authenticated update from 148.7 to 66.0 µs in native C. The full chain runs in real time, with no deadline miss over 552 windows (worst case 1.8% of the 171 ms window), and feature extraction dominates its cost. The model reaches 98.2% on unseen segments but generalizes poorly to unseen fault severities and to real damage of unseen Paderborn bearings, which makes field updates a requirement.

Spatiotemporal deep learning models, like Graph Neural Networks (GNNs), Transformers, and selective State Space Models (Mamba), have achieved impressive performance in electroencephalogram (EEG) decoding and affective computing. However, their generalization performance often degrades severely under subject-independent Leave-One-Subject-Out (LOSO) cross-validation protocols. This generalization drop is often attributed to generic domain shifts in standard Brain–Computer Interface (BCI) literature, and is tackled by parameter-heavy adaptations. In contrast, this paper proposes a unified mathematical diagnostic framework to audit and measure the underlying representation and geometric collapse in spatiotemporal brain–computer interfaces. More concretely, we formalize: (1) Topological over-smoothing under volume conduction through Graph Dirichlet Energy bounds indicating GCNs as low-pass filters that smooth localized electrode variations; (2) representation collapse through the Normalized Rank Uniformity Index (NRUI) based on the Shannon Entropy of latent covariance eigenvalues, that distinguishes between dimensional and semantic collapse; and (3) geometric manifold distortions under subject domain shifts on the Symmetric Positive Definite (SPD) Riemannian manifold under the Affine-Invariant Riemannian Metric (AIRM) projection. Auditing these diagnostic metrics on canonical models across DEAP, DREAMER, and SEED, we demonstrate why standard spatiotemporal architectures suffer from performance collapse in cross-subject configurations. We provide BCI engineers with a tangible mathematical blueprint to design robust, collapse-resistant decoders.

Automatic emotion recognition based on EEG has been a key research frontier in recent years, involving the direct extraction of emotional states from brain dynamics. However, existing deep learning approaches often treat EEG either as a sequence or as a static spatial map, thereby failing to jointly capture the temporal evolution and spatial dependencies underlying emotional responses. To address this limitation, we propose an Interpretable Residual Spatio-Temporal Graph Attention Network (IRSTGANet) that integrates temporal convolutional encoding with residual graph-attention blocks. The temporal module enhances short-term EEG dynamics, while the graph-attention layers learn adaptive node connectivity relationships and preserve contextual information through residual links. Evaluated on the DEAP and SEED datasets, the proposed model achieved exceptional performance on valence and arousal, as well as four-class and nine-class classification on the DEAP dataset and on the three-class SEED dataset, exceeding state-of-the-art methods. These results demonstrate that combining temporal enhancement with residual graph attention yields both improved recognition performance and interpretable insights into emotion-related neural connectivity.

The need for efficient and real-time traffic sign recognition has become increasingly important as autonomous vehicles and Advanced Driver Assistance Systems (ADASs) continue to evolve. This study introduces TSRACE-AI, a system that accelerates traffic sign recognition by combining hardware and software in a hybrid architecture deployed on the PYNQ-Z2 FPGA platform. The design employs the Deep Learning Processing Unit (DPU) for hardware acceleration and incorporates 8-bit fixed-point quantization to enhance the performance of the CNN model. The proposed system achieves a 98.85% reduction in latency and a 200.28% increase in throughput compared to similar works, with a trade-off of a 90.35% decrease in power efficiency. Despite this trade-off, the system excels in latency-sensitive applications, demonstrating its suitability for real-time decision-making. By balancing speed and power efficiency, TSRACE-AI offers a compelling solution for integrating traffic sign recognition into ADAS, paving the way for enhanced autonomous driving capabilities.