Xiangjun Lu

In three-dimensional packaging architectures, the Through-Silicon Via-Redistributed Layer (TSV-RDL) interconnect structure serves as the critical conductive pathway and is continuously subjected to combined thermo-electric coupling loads, making it a vulnerable zone for electromigration failures. This research adopts a multidimensional methodology to analyze the influencing factors of electromigration in TSV-RDL. First, the study designs electromigration acceleration experiments based on the dual factors of temperature and current density to establish the time-varying resistance characteristic curves of the TSV-RDL. Second, scanning electron microscopy is employed to characterize the failure interfaces and to analyze the morphological differences between thermally dominant and electrically dominant failure modes. Finally, a thermal-electrical-mechanical multiphysics coupling model is constructed using the ANSYS Workbench platform. In conclusion, the study unequivocally demonstrates that the failure mechanisms in TSV-RDL structures are governed by two distinct regimes, dictated by the dominant driving force. The invariant locations of current crowding and stress concentration serve as inherent weaknesses of the structure. Crucially, the research establishes that the current-density-dominated regime leads to gradual, predictable degradation, whereas the temperature-dominated regime triggers rapid, catastrophic failure. These findings provide a critical foundation for designing reliable 3D integrations: by actively controlling the operational regime to favor current-density dominance, designers can significantly extend the interconnect lifespan. Furthermore, the identified failure hotspots offer precise targets for structural reinforcement and reliability monitoring.

The conventional reliability tests for through-silicon via-redistributed layer (TSV-RDL) interconnect structure typically require destructive inspection methods for defect characterization. Meanwhile, while capable of detecting major defects, the nondestructive dc resistance characterization lacks the sensitivity to reveal subtle degradation under high-frequency operating conditions. Scatter parameters (S-parameters), in contrast, demonstrate earlier and more sensitive failure characterization capabilities in high-frequency applications. This study systematically analyzes the impact of electromigration failures on the RF characteristics of TSV-RDL through combined experimental and simulation approaches, proposing a nondestructive inspection method based on S-parameters for electromigration reliability assessment. The postelectromigration of TSV-RDL exhibit two types of S-parameter characteristics: the reversal curves of open-circuit defect (caused by rapid void coalescence under high-temperature stress) and curves that closely resemble the defect-free morphology. The open-circuit defects induce strong reflection of low-frequency signals, whereas increasing frequency enhances coupling–forming reversal curves characterized by rising S₂₁ and falling S₁₁. The S₁₁ profile varies with defect location, whereas S₁₁ can localize open-circuit defects with resolution limitations at TSV pitches $\lt 100~\mu $ m, combining it with S₂₁ enables precise defect mapping and structural analysis. Additionally, S₂₁ parameters provide preliminary defect size assessment.

The potential of high‐nickel‐layered LiNi _{1– x – y} Co _y Mn _z O ₂ (with 1– x – y > 0.6, NCM) cathode as frontrunners for the high energy‐density lithium‐ion batteries (LIBs) lies in their high theoretical specific capacity and working potential. However, an inherent challenge arises from the formation of residual lithium compounds, leading to issues such as capacity deterioration, and suboptimal to deposition rage characteristics. Herein, this study leverages the prowess of plasma‐enhanced atomic layer deposition (ALD) technology to effectively coat LiNi _0.8 Co _0.1 Mn _0.1 O ₂ (NCM811) particles with a lithium reactive Co ₃ O ₄ layer. Consequently, these interventions yield tangible enhancements in the cycling performance and thermal stability of NCM811 materials. At a current density of 1 C, the initial specific capacity witnesses a noteworthy ascent from 152.9 mAh g ⁻¹ for the uncoated electrode to 169.1 mAh g ⁻¹ for the NCM811 cathode with Co ₃ O ₄ coating. After cycling for 200 cycles, the capacity retention rates register at 55.79% and 80.84%, respectively, for the uncoated and coated electrodes. Notably, the impact of Co ₃ O ₄ extends to bolstering the thermal stability of NCM811. In essence, this study harnesses ALD technology to cultivate a Co ₃ O ₄ ‐coated environment for NCM811, elevating cycling performance and enhancing thermal stability. These advancements hold profound implications for the evolution of LIB technology.

3D-integrated GaN power modules can effectively reduce parasitic parameters and enhance the power system’s performance. However, the heat from each power chip during operation can lead to a mutual thermal coupling effect, potentially causing performance drift of the GaN power chips. This work investigates the impact of the thermal coupling effect in a 3D-integrated GaN power module on the characteristics of its GaN power chips. The GaN power chips’ characteristics are measured before and after the other power chips in the 3D-integrated GaN power module and after applying V_GS/V_DS = 3 V/1 V for 60 s. The results indicate that the thermal coupling effect in 3D-integrated GaN power modules can cause a rightward shift in the threshold voltage, reduce the response speed and on-state current, and also increase the leakage current of GaN power chips. In severe cases, the threshold voltage drift can reach up to 0.26 V, the device’s response time can increase by as much as 217 μs, the on-state current can decrease by 1.7 A, and the off-state leakage current can increase by more than 80 times. The impact of the thermal coupling effect is related to the direction of heat flow and the distance between chips. The closer the chips are to each other, the stronger the thermal coupling. It has a greater impact on the performance of chips near the bottom substrate and a lesser impact on the performance of chips at the top of the module. Typically, the influence of the thermal field generated by two chips working simultaneously is more significant than that of the thermal field generated by a single chip working alone.

The thermal through-silicon-via (TTSV) has a serious thermal stress problem due to the mismatch of the coefficient of thermal expansion between the Si substrate and filler metal. At present, the thermal stress characteristics and strain mechanism of TTSV are mainly concerned with increases in temperature, and its temperature range is concentrated between 173 and 573 K. By employing finite element analysis and a device simulation method based on temperature-dependent material properties, the impact of TTSV thermal stress on metal-oxide-semiconductor field-effect transistor (MOSFET) properties is investigated under cooling down from room temperature to the ultra-low temperature (20 mK), where the magnitude of thermal stress in TTSV is closely associated with the TTSV diameter and results in significant tension near the Cu-Si interface and consequently increasing the likelihood of delamination and cracking. Considering the piezoresistive effect of the Si substrate, both the TTSV diameter and the distance between TTSV and MOSFET are found to have more pronounced effects on electron mobility along [100] crystal orientation and hole mobility along [110] crystal orientation. Applying a gate voltage of 3 V, the saturation current for the 45 nm-NMOS transistor oriented along channel [100] experiences a variation as high as 34.3%. Moreover, the TTSV with a diameter of 25 μm generates a change in MOSFET threshold voltage up to −56.65 mV at a distance as short as 20 μm. The influences exerted by the diameter and distance are consistent across carrier mobility, saturation current, and threshold voltage parameters.

Current research on the transmission characteristics of Through Silicon Via - Redistribution Layer (TSV-RDL) interconnects is basically limited to the single-pair interconnect (a device with two TSVs connected by an RDL line is referred to as 1-pair), which is obviously insufficient for highly integrated three-dimensional packaging. Thus, this paper aims to simulate the actual long-chain interconnects by establishing an equivalent circuit model of multi-pair TSV-RDL interconnects in order to explore their transmission characteristics. First, the equivalent circuit model of long-chain Ground-Signal-Ground type TSV-RDL interconnects is established based on the correlation between single-pair and multi-pair interconnects. Second, the transmission performance of long-chain interconnects is investigated by analyzing the reasons for the differences in insertion loss of various length test vehicles in the frequency band from 0.01 to 40 GHz. Compared to RDL lines, TSVs have greater impact on the overall loss. The resistance of interconnects and the capacitance of the insulating layer at low-frequency, the capacitance and conductance associated with the conductive substrate in the mid-frequency range, as well as the inductance in the high frequency region all play pivotal roles in impedance changes in their respective domains. Finally, the above analysis points out the optimization of the long-chain interconnect by increasing its length while avoiding excessive inductance due to RDL lines in order to reduce the use of TSVs and thus improve the overall transmission performance.

The combined use of Through Silicon Via (TSV) and metal lines, referred to as TSV-metal lines, is an essential structure in three-dimensional integrated circuits. In-depth research into the electromigration failure mechanism of TSV and the microstructure evolution can serve as theoretical guidance for optimizing three-dimensional stacking. This article conducted electromigration experiments on TSV-metal line structural samples at current densities of 1.0 × 10⁵ A/cm², 5 × 10⁵ A/cm², and 1 × 10⁶ A/cm². Additionally, Electron Back Scattered Diffraction (EBSD) technology was employed to systematically investigate the microstructural evolution of the TSV-metal line structure profiles before and after the application of electrical testing. The results indicate that the current induces a change in the crystal orientation at the TSV-metal interface (TSV/metal interface) and the bottom metal line. This phenomenon notably depends on the initial angle between the grain orientation and the current flow direction. When the angle between the current direction and the grain orientations [001] and [010] is relatively large, the crystals are more likely to deviate in the direction where the angle between the grain orientation and the current is smaller. This is because, at this point, the current direction is precisely perpendicular to the crystal plane family, where the atomic density is lowest, and the energy required for electron transport is minimal. Therefore, the current readily rotates in the direction of this crystal orientation. Before the electromigration tests, areas with a high level of misorientation were primarily concentrated at the TSV/metal interface and the corners of the TSV-metal line. However, these areas were found to be more prone to developing voids after the tests. It is conjectured that the high misorientation level leads to elevated stress gradients, which are the primary cause of cracking failures in the TSV-metal line. As the current density increases from 5 × 10⁵ A/cm² to 1 × 10⁶ A/cm², the electromigration failure phenomena in the TSV become even more severe.

The cohesive performance and durability of the bonding layer with semiconductor substrates are of paramount importance for realizing the high thermal conductivity capabilities of diamond. Utilizing electron beam evaporation and the room-temperature, low-pressure bonding process, robust adhesion between diamonds and silicon substrates has been achieved through the application of the metal modification layer comprised of Ti/Cu/Ti/Au (5/300/5/50 nm). Characterization with optical microscopy and atomic force microscopy reveals the uniformity and absence of defects on the surface of the deposited layer. Observations through X-ray and scanning acoustic microscopy indicate no discernible bonding defects. Scanning electron microscopy observation and energy-dispersive spectroscopy analysis of the fracture surface show distinct fracture features on the silicon substrate surface, indicating that the bonding strength of the Ti/Cu/Ti/Au metallization layer surpasses that of the base material. Furthermore, the fracture surface exhibits the presence of Cu and trace amounts of Ti, suggesting that the fracture also occurs at the interface between Ti and Cu. Characterization of the metal modification layer using X-ray diffraction reveals significant lattice distortion in the Ti layer, leading to noticeable stress accumulation within the crystalline structure. Thermal–mechanical fatigue simulations of the Ti/Cu/Ti/Au metal modification layer indicate that, owing to the difference in the coefficient of thermal expansion, the stress exerted by the Cu layer on the Ti layer results in the accumulation of fatigue damage within the Ti layer, ultimately leading to a reduction in its strength and eventual failure.

To study the working performance of 3D stacked chips, a double-layer stacked GaN MISHEMTs structure was designed to study the electro-thermal characteristics and heat transfer process of stacked chips. Firstly, the electrical characteristics of double-layer and single-layer GaN MISHEMTs are compared at room temperature. Under the same conditions, the output current of double-layer GaN MISHEMTs is twice that of single-layer GaN MISHEMTs, but its off-state current is much higher than that of a single-layer device. Meanwhile, there is no significant difference between the threshold voltages of the double-layer and single-layer GaN MISHEMTs. Then, the effect of temperature on the electrical characteristics of double-layer GaN MISHEMTs is also investigated. When the temperature increased from room temperature to 150 °C, the device’s threshold voltage gradually shifted negatively, the output current of the device decreased, and the off-state current of the device increased. Furthermore, a thermal resistance network model has been established to analyze the thermal characteristics of the stacked GaN MISHEMTs. The relative error between the results calculated according to the model and the experimental results does not exceed 4.26%, which verified the correctness and accuracy of the presented model to predict the temperature distribution of the stacked GaN MISHEMTs.