Kalyan Koley

This work introduces a δ p ⁺ Si _{1− x} Ge _x pocket and dual-stacked source (DS) silicon on insulator(SOI) tunnel field-effect transistor (TFET) incorporating a ferroelectric trench-gate dielectric material (TG-Fe-SOI-TFET), explores its geometric parameter variation and shows an enhancement over the baseline and TG-SOI-TFET using Sentaurus technology computer-aided design. The ferroelectric (FE) gate stack utilizes negative capacitance as a technique to reduce power supply, intrinsic voltage amplification, as well as minimization of power dissipation. Results indicate that inclusion of the FE layer boosts the internal voltage and strengthens the electric field value at the source-channel tunneling junction, leading to high ON current in the order of 10 ⁻³ A µ m ⁻¹ and an improved band-to-band-tunneling rate of 8.51 × 10 ³⁰ 1/cm ³ s. This improvement also results in a higher I _ON /I _OFF ratio (1.22 × 10 ¹⁴ ) and a steeper subthreshold slope of 9.18 mV dec ⁻¹ when compared to the baseline TG-SOI-TFET. The TG-Fe-SOI-TFET also shows a peak operating frequency of 96 GHz, making it suitable for RF applications. Additionally, we have analyzed the effect of the FE layer inclusion on various linearity performance figures of merit, including g _m2 , g _m3 , VIP2, VIP3, IIP3 , and the 1-dB compression point. Improved linearity characteristics confirm that the proposed TG-Fe-SOI-TFET device is suitable for distortion-free operation. Employing a buffer layer in the TFET enhances DC/RF performance, and a comparative analysis of SiO ₂ , Al ₂ O ₃ , and HfO ₂ dielectrics has been performed. The design space of the TFET was explored by analyzing performance using different material choices for each of the layers. Additional optimizations have been made and showcased to the geometric parameter variations, including buffer layer thickness ( t _OX ), the Si & Ge layer thickness in the DS and FE layer thickness ( t _FE ), all of which are crucial for improving both DC and RF performance. Variation of temperature in the 300–400 K range has been studied and minimal temperature sensitivity on device performance has been found. Furthermore, the impact of positive and negative ITCs on the performance of the proposed TFET is systematically investigated by incorporating a fixed trap density at the channel-gate oxide interface.

In this manuscript, a novel TFET design named Hetero-Dielectric Step Shaped Double Gate TFET on SELBOX substrate (HD-SSDG-SELBOX TFET) has been proposed to improve the functional capability of the device using the Sentaurus TCAD tool. The novelty of the suggested device is the stepped gate on SELBOX substrate which provides negligible ambipolarity for the negative supply voltage at drain/channel junction as well improve the I ON /I OFF ratio. The suggested structure employs a heterodielectric gate oxide and an overlapped gate pocket, which together enhances the tunneling rate, thereby increasing the drain current. Additionally, the inclusion of a SiGe pocket introduced at the source side enhances the tunneling probability of charge carriers, further boosting the ON-state current. The alteration of RF metrics such as transconductance (g m ), parasitic capacitances, cut-off frequency(f T ), maximum oscillating frequency (f max ), transconductance generation factor (TGF), Intrinsic delay, gain bandwidth product (GBP), and transconductance frequency product (TFP) with temperature have also been studied. Moreover, the electrical noise characteristics of the HD-SSDG-SELBOX TFET are analyzed over 1 MHz-10 GHz to assess its feasibility, and the results are compared. The suggested TFET structure demonstrates an impressive I ON /I OFF current ratio of 1.78 × 10¹⁴, with an I ON of 3.84 × 10⁻ 4 A/μm and an I OFF of 2.15 × 10⁻ 18 A/μm. It also exhibits a significantly low SS of 16 mV/dec, suppressed ambipolar conduction extending to a higher negative bias region, and enhanced transconductance (g m ) (2.25 × 10 -4 S) along with higher values of f T (1.58×10 11 Hz) and f max (2.42×10 12 Hz). A detailed evaluation of performance parameters provides valuable insights for device design. This implies that the suggested device exhibits improved reliability compared to standard TFETs in low-power operation under elevated temperatures.

This report presents a III-V gate-all-around tunnel field-effect transistor (GAA TFET)-based label-free biosensor for the detection of breast cancer and prostate cancer in females and males. The highly sensitive region of the TFET device has been targeted for sensing the bioanalytes (BAs). The biomarkers considered for detection are a clinically relevant concentration of c-erbB-2 for breast cancer and prostate-specific antigen (PSA) for prostate cancer serum. Since the subthreshold region is highly sensitive to any minor changes in serum concentrations, therefore, this report aims to utilize the subthreshold region of the device for BAs sensing. The transconductance generation factor ( g_m/I_DS ) has been chosen as the sensing metric as it encompasses the low bias region (linear region) of the device, which consumes low power for BAs detection. The validity of g_m/I_DS as a sensing approach has been confirmed through various figures-of-merit, including space charge, band gap fluctuations, lateral electric field, depletion capacitances, and transfer characteristics of the device. The feasibility of the g_m/I_DS -based sensing approach has been demonstrated by qualitative analysis, specifically by varying the cavity lengths of the device. Numerical analysis using a charge deduction-based methodology has been employed, and the results align with the theoretical understanding of the device for both healthy and diseased males and females.

The effects of negative bias temperature instability (NBTI) on emerging tunnel FET (TFET) devices are setting of important reliability concern for analog/digital circuit design. In this work, NBTI effects in gate-all-around tunnel FET (GAA TFET) devices have been thoroughly analyzed and the unstressed p-type GAA TFET transfer characteristics are calibrated with the experimentally published data to tune the models used for the numerical analysis. The GAA device is stressed for different time durations and for different temperatures to analyze the capture and emission probabilities of the trapped charges. The effect of oxide trapping, interface trapping, and trapping of charges at several regions in the channel are analyzed individually, as well as collectively. The sub-threshold voltage of the TFET device is also investigated and it has been found that the change in the sub-threshold slope is not at all degraded by NBTI stress.

Many times, the fabricated cylindrical gate-all-around tunnel FET (GAA TFET) has an uneven radius due to several etching and deposition processes involved while fabricating the device, which show notable variations in the performance of the device. In this report, III–V uneven GAA TFET is studied by considering the uneven radius as elliptical in shape for all possible variations, which shows a significant impact on analog and RF figure of merits (FOMs). The performance of the optimized devices is compared with their circular structure and with their maximum deviation in elliptical geometry for all possible variations in device channel and gate oxide. The variations in its device channel and gate oxide have shown a significant impact on the performance of the device. The analog and RF FOMs are studied, including the transconductance generation factor (g_m/I_DS), intrinsic gain (g_mR_O), capacitances (C_GS, C_GD), cut-off frequency (f_T), and gate delay (τ_m).

The heavy-ion analysis is a single-event-effect (SEE) that produces a single-event-transient (SET) pulse of current. In this work, the analysis was done to observe the maximum impact of heavy-ions on a calibrated double-gate tunnel field-effect transistor (DG-TFET) taken as a device under test (DUT). The impact of heavy-ions on DG-TFET is compared with the previous work done for different TFETs. The ions are directed to strike vertically at five different positions; source, source-body junction, body, drain-body junction, and the drain region of DG-TFET. The analysis is done by observing the heavy-ion generation rate, heavy-ion charge density, and transient current for the strike of the ion at different locations on the DUT and at different linear energy transfer (LET) values with the help of physics-based numerical simulation. In the study, a detailed analysis of the transient current due to a heavy-ion strike in the body region is reported, and this transient current is compared with the existing reported data for different FETs. Bipolar gain of the device is also observed for a heavy-ion strike in the body region, which is an important parameter for analyzing SEE. The findings in this study can give a new insight into SEE in TFET devices and can also provide guidelines for radiation-hardened applications for TFET-based circuits.