Xuanyao Fong

Electronic solvers for combinatorial optimization problems (COPs) have attracted significant research interest as a poor man’s replica of the costly quantum computers. Though existing works have shown their great potential in speed and energy/area efficiency, two primary challenges remain: i) efficient optimization of the circuit-level parameter to improve the system robustness; and ii) extensibility to solving the full portfolio of COPs, beyond binary variable and second-order coupling. They are important for system scaling and solving general COPs, and rely on a comprehensive hardware-software co-optimization framework. This work focuses on a framework unifying the representations of various COPs on bistable latch-based circuit building blocks, named Unified Latch-based COP Solver (ULTER) and using a corresponding co-optimization approach to perform system-level optimizations. The ULTER system is comprehensively evaluated on the MaxCut, XORSAT, NAE-SAT, and graph coloring problems, greatly extending the robustness and generality of the existing analog COP solvers.

Large Language Model (LLM) inference challenges memory/computing organization and dataflow optimization on traditional hardware stacks due to its various attention mechanisms and autoregressive structure. In-memory computing (IMC) and near-memory computing (NMC) architectures have emerged as potential solutions to reduce the memory burden in LLMs. However, efficient LLM orchestration on IMC/NMC, as well as dedicated IMC/NMC architecture optimization, are interrelated, encompassing a hardware-software co-design space of a myriad of parameters, which still remains largely underexplored. This work provides a joint architecture-dataflow exploration (JADE) framework that covers both architectural factors on computing/memory/communication, and algorithmic factors on LLM dataflow. We identify key configurations in four categories: computing and memory organization, interconnection topology, matrix multiplication (MM) unrolling and mapping, and attention mechanism. A unified MM representation enables flexible unrolling and mapping on various architectural organizations. Dataflow is routed based on the collective communication patterns inherent in the distributed LLMs and the features of common topologies. Finally, case studies show the design tradeoffs between key design options and provide insights into both homogeneous and heterogeneous IMC/NMC design for LLMs.

Deploying multi-billion-parameter Large Language Models (LLMs) on modern AI accelerators requires both low-latency communication and energy-efficient computation. Emerging heterogeneous in-memory computing (IMC) architectures offer a promising solution by co-locating compute and storage, thereby reducing data movement and power consumption. However, efficiently partitioning and distributing model workloads across cores remains a key open challenge in multi-chiplet, network-based accelerator systems for LLMs, as it directly impacts the workload’s performance and hardware utilization. We present a heterogeneous multi-chiplet accelerator architecture accompanied by a co-designed fine-grained hardware–software stack. This stack incorporates custom algorithms for LLM partitioning, workload mapping, and identification of hardware configurations that ensure efficient execution. In contrast to prior work, our methodology adopts a bottom-up perspective, addressing execution from the core level up to the chiplet-level coordination to enable scalability and flexible dataflows. Moreover, we assess and recommend hardware setups optimized for different classes of LLMs, offering practical guidance for selecting architectures best suited to specific models. Through cycle-accurate experimental evaluation, we demonstrate that our approach achieves up to 4× higher token throughput and 30× better energy efficiency compared to state-of-the-art H100 GPUs on the same workloads.

Large Language Models (LLMs) exhibit substantial parameter redundancy, particularly in Feed-Forward Networks (FFNs). Existing pruning methods suffer from two primary limitations. First, reliance on dataset-specific calibration introduces significant data dependency and computational overhead. Second, being predominantly static, they fail to account for the evolving subset of knowledge neurons in LLMs during autoregressive generation as the context evolves. To address this, we introduce DART, i.e., Dynamic Attention-Guided Runtime Tracing), a lightweight, training-free method that performs on-the-fly context-based pruning. DART monitors shifts in attention score distributions to infer context changes, dynamically updating neuron-level masks to retain salient parameters. Across ten benchmarks, DART outperforms prior dynamic baseline, achieving accuracy gains of up to 14.5% on LLAMA-3.1-8B at 70% FFN sparsity. Furthermore, DART achieves up to 3x better ROUGE-L scores with respect to static-masked pruning on summarization tasks, with its performance comparable to the original dense models. We conclusively demonstrate that the proposed framework effectively adapts to diverse semantic contexts, preserves model capabilities across both general and domain-specific tasks while running at less than 10MBs of memory for LLAMA-3.1-8B(16GBs) with 0.1% FLOPs overhead. The code is available at https://github.com/seeder-research/DART.

While three-dimensional magnetic recording (3DMR) multiplies the capacity of hard disk drives by stacking multiple recording layers perpendicularly, it also complicates the magnetization interactions between adjacent bits and introduces more interference. In this work, we determine the detrimental bit-pair patterns that induce severe writing interference in dual-layer 3DMR via micromagnetic simulation, and we propose a design of constrained codes to enhance recording reliability by restricting these patterns. Our results show that the coding scheme improves the media signal-to-noise ratio (SNR) by up to 17.93% and reduces the post-detection bit error rate (BER) by up to 99.67% to nearly 10⁻⁵ with user areal density between 1.6 and 3.2 Tb/in².

In this work, we experimentally study intrinsic variability behaviors in back-end-of-line (BEOL)-compatible oxide-semiconductor ferroelectric field-effect transistors (OS FeFETs) under aggressive channel-length scaling down to 40 nm. Measurements on ZnO-channel OS FeFETs reveal two distinct trends: (i) a monotonic increase in coefficient of variance (COV) in drain-current during full switching (FSW), primarily governed by ferroelectric (FE) and process-induced variations; and (ii) an unexpected non-monotonic COV behavior under partial switching (PSW), attributed to stochastic percolation path formation on top of the process and ferroelectric (FE) variations including grain inhomogeneity (GI) in FSW. We modeled the DTD variations of OS FeFETs in FSW and PSW to gain physical insights into the origin of these trends, which are important for variation-aware device scaling optimization.

The ferroelectric field-effect transistor (FeFET) is a promising memory device technology due to desirable attributes such as fast access times, high memory cell density, good endurance, compatibility with CMOS process, and impressive scalability. While previous research has explored the impact of process variations at the device level, their effects on circuit behavior have not been comprehensively investigated due to a lack of a framework for analyzing FeFET bit-cell failures at the circuit-level, which we present in this work. We studied the process parameters including ferroelectric (FE) layer thickness, channel length, channel width, and effective oxide thickness of a FeFET bit-cell. The correlations of each failure event and the write pulse voltage and write pulse width are studied. Our results show that the voltage applied on the FeFET bit-cell dominates the performance of the bit-cell for both write and read operations.