Francesca Palumbo
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Francesca Palumbo has a total of 72 co-authors. Here are the top co-authors by number of shared publications:
- Luigi Raffo
University of Cagliari
10 shared publications - Carlo Sau
University of Cagliari
9 shared publications - Claudio Rubattu
University of Sassari
6 shared publications - Francesco Ratto
University of Cagliari
6 shared publications Luigi Raffo
University of Cagliari, Italy
5 shared publications- Danilo Pani
Department of Electrical and Electronic Engineering, University of Cagliari, Cagliari, Italy
4 shared publications
Latest Publications
- 30 June 2026
- Published by Springer Nature
- p. 365-370
MYRTUS: A Preliminary Assessment of The Heterogeneous Computing Continuum Infrastructure
- 30 June 2026
- Published by Springer Nature
- p. 365-370
MYRTUS: A Preliminary Assessment of The Heterogeneous Computing Continuum Infrastructure
- 17 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Embedded Systems Letters
- Vol. PP (19430663) , 1
Adaptive CNN Acceleration on FPGAs: Closing the Gap With State-of-the-Art Solutions
This paper presents a comparative study of a design flow for generating Convolutional Neural Network (CNN) accelerators on Field Programmable Gate Arrays (FPGAs), based on an extension of the Multi-Dataflow Composer (MDC) tool, against established frameworks: HLS4ML, FINN and Vitis AI. The proposed design flow explores a previously untapped area of the design space: runtime reconfigurable accelerators. By enabling runtime reconfigurability, it provides adaptivity support, filling a gap in current FPGA-based accelerator design options. The analysis focuses on the trade-offs and benefits of each approach, particularly regarding performance and adaptivity.
- 17 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Embedded Systems Letters
- Vol. PP (19430663) , 1
Adaptive CNN Acceleration on FPGAs: Closing the Gap With State-of-the-Art Solutions
This paper presents a comparative study of a design flow for generating Convolutional Neural Network (CNN) accelerators on Field Programmable Gate Arrays (FPGAs), based on an extension of the Multi-Dataflow Composer (MDC) tool, against established frameworks: HLS4ML, FINN and Vitis AI. The proposed design flow explores a previously untapped area of the design space: runtime reconfigurable accelerators. By enabling runtime reconfigurability, it provides adaptivity support, filling a gap in current FPGA-based accelerator design options. The analysis focuses on the trade-offs and benefits of each approach, particularly regarding performance and adaptivity.
- Open Access
- 8 November 2025
- Published by Elsevier in Journal of Systems Architecture
- Vol. 170
An FPGA-based accelerator design methodology for smart UAVs in precision agriculture: A case study
- 8 November 2025
- Published by Elsevier in Journal of Systems Architecture
- Vol. 170
Open AccessAn FPGA-based accelerator design methodology for smart UAVs in precision agriculture: A case study
- Open Access
- 19 May 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Open Journal of the Industrial Electronics Society
- Vol. 6, 898-914
Integrating FPGA-Based Acceleration in Industrial Motion Control System
Manufacturing processes increasingly depend on advanced production machinery that must deliver high quality and large volumes. This applies to die-bonding machines as well that, especially at the time being after the years of shortage, need to meet very high standards of speed and accuracy. To achieve this, these devices are exploring the use of computer vision algorithms for automatic recognition of wafer positioning and die size. Nevertheless, these systems are typically managed by software-only solutions, which may fall short under stringent execution time requirements. A promising solution is the use of heterogeneous platforms, combining general-purpose processors with reconfigurable hardware. Such platforms offer the flexibility to handle both software tasks, which benefit from operating system support, and critical functions requiring hardware acceleration. This paper presents a closed-loop implementation of a vision-based multi-sensor control system for an industrial application. The implementation exploits the capabilities of System on Module (SoM) technologies to provide flexible I/O and software execution coupled with computing acceleration for the vision algorithm on the reconfigurable Field Programmable Gate Array (FPGA) fabric. The FPGA coprocessor has been designed leveraging the High-Level Synthesis (HLS) technology and optimized on a dataset of 10k realistic images to meet the industrial use case's performance, communication, and accuracy requirements. Moreover, the resulting accelerator performance and resource utilization demonstrate the possibility of reaching state-of-the-art metrics of handwritten hardware designs while allowing for higher abstraction and productivity of the design process.
- 19 May 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Open Journal of the Industrial Electronics Society
- Vol. 6, 898-914
Open AccessIntegrating FPGA-Based Acceleration in Industrial Motion Control System
Manufacturing processes increasingly depend on advanced production machinery that must deliver high quality and large volumes. This applies to die-bonding machines as well that, especially at the time being after the years of shortage, need to meet very high standards of speed and accuracy. To achieve this, these devices are exploring the use of computer vision algorithms for automatic recognition of wafer positioning and die size. Nevertheless, these systems are typically managed by software-only solutions, which may fall short under stringent execution time requirements. A promising solution is the use of heterogeneous platforms, combining general-purpose processors with reconfigurable hardware. Such platforms offer the flexibility to handle both software tasks, which benefit from operating system support, and critical functions requiring hardware acceleration. This paper presents a closed-loop implementation of a vision-based multi-sensor control system for an industrial application. The implementation exploits the capabilities of System on Module (SoM) technologies to provide flexible I/O and software execution coupled with computing acceleration for the vision algorithm on the reconfigurable Field Programmable Gate Array (FPGA) fabric. The FPGA coprocessor has been designed leveraging the High-Level Synthesis (HLS) technology and optimized on a dataset of 10k realistic images to meet the industrial use case's performance, communication, and accuracy requirements. Moreover, the resulting accelerator performance and resource utilization demonstrate the possibility of reaching state-of-the-art metrics of handwritten hardware designs while allowing for higher abstraction and productivity of the design process.
- 28 January 2025
- Published by Springer Nature
- p. 85-96
ONNX-To-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
- 28 January 2025
- Published by Springer Nature
- p. 85-96
ONNX-To-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
- Open Access
- 7 May 2024
- Published by Association for Computing Machinery (ACM)
- p. 101-106
MYRTUS: Multi-layer 360° dYnamic orchestration and interopeRable design environmenT for compute-continUum Systems
The MYRTUS Horizon Europe Project embraces the principles of the EUCloudEdgelOT Initiative and integrates edge, fog and cloud computing platforms, leveraging a cognitive engine based on swarm intelligence and federated learning to orchestrate collaborative distributed and decentralised components.
- 7 May 2024
- Published by Association for Computing Machinery (ACM)
- p. 101-106
Open AccessMYRTUS: Multi-layer 360° dYnamic orchestration and interopeRable design environmenT for compute-continUum Systems
The MYRTUS Horizon Europe Project embraces the principles of the EUCloudEdgelOT Initiative and integrates edge, fog and cloud computing platforms, leveraging a cognitive engine based on swarm intelligence and federated learning to orchestrate collaborative distributed and decentralised components.
- Open Access
- 9 May 2023
- Published by Association for Computing Machinery (ACM)
- p. 358-363
A multithread AES accelerator for Cyber-Physical Systems
- 9 May 2023
- Published by Association for Computing Machinery (ACM)
- p. 358-363
Open AccessA multithread AES accelerator for Cyber-Physical Systems
- Open Access
- 26 April 2023
- Published by Springer Nature in Journal of Signal Processing Systems
- Vol. 95 (9) , 1091-1113
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators
Image and video processing are one of the main driving application fields for the latest technology advancement of computing platforms, especially considering the adoption of neural networks for classification purposes. With the advent of Cyber Physical Systems, the design of devices for efficiently executing such applications became more challenging, due to the increase of the requirements to be considered, of the functionalities to be supported, as well as to the demand for adaptivity and connectivity. Heterogeneous computing and design automation are then turning into essential. The former guarantees a variegated set of features under strict constraints (e.g., by adopting hardware acceleration), and the latter limits development time and cost (e.g., by exploiting model-based design). In this context, the literature is still lacking adequate tooling for the design and management of neural network hardware accelerators, which can be adaptable and customizable at runtime according to the user needs. In this work, a novel almost automated toolchain based on the Open Neural Network eXchange format is presented, allowing the user to shape adaptivity right on the network model and to deploy it on a runtime reconfigurable accelerator. As a proof of concept, a Convolutional Neural Network for human/animal classification is adopted to derive a Field Programmable Gate Array accelerator capable of trading execution time for power by changing the resources involved in the computation. The resulting accelerator, when necessary, can consume 30% less power on each layer, taking about overall 8% more time to classify an image.
- 26 April 2023
- Published by Springer Nature in Journal of Signal Processing Systems
- Vol. 95 (9) , 1091-1113
Open AccessAn Automated Design Flow for Adaptive Neural Network Hardware Accelerators
Image and video processing are one of the main driving application fields for the latest technology advancement of computing platforms, especially considering the adoption of neural networks for classification purposes. With the advent of Cyber Physical Systems, the design of devices for efficiently executing such applications became more challenging, due to the increase of the requirements to be considered, of the functionalities to be supported, as well as to the demand for adaptivity and connectivity. Heterogeneous computing and design automation are then turning into essential. The former guarantees a variegated set of features under strict constraints (e.g., by adopting hardware acceleration), and the latter limits development time and cost (e.g., by exploiting model-based design). In this context, the literature is still lacking adequate tooling for the design and management of neural network hardware accelerators, which can be adaptable and customizable at runtime according to the user needs. In this work, a novel almost automated toolchain based on the Open Neural Network eXchange format is presented, allowing the user to shape adaptivity right on the network model and to deploy it on a runtime reconfigurable accelerator. As a proof of concept, a Convolutional Neural Network for human/animal classification is adopted to derive a Field Programmable Gate Array accelerator capable of trading execution time for power by changing the resources involved in the computation. The resulting accelerator, when necessary, can consume 30% less power on each layer, taking about overall 8% more time to classify an image.
- Open Access
In-Field Automatic Detection of Grape Bunches under a Totally Uncontrolled Environment
An early estimation of the exact number of fruits, flowers, and trees helps farmers to make better decisions on cultivation practices, plant disease prevention, and the size of harvest labor force. The current practice of yield estimation based on manual counting of fruits or flowers by workers is a time consuming and expensive process and it is not feasible for large fields. Automatic yield estimation based on robotic agriculture provides a viable solution in this regard. In a typical image classification process, the task is not only to specify the presence or absence of a given object on a specific location, while counting how many objects are present in the scene. The success of these tasks largely depends on the availability of a large amount of training samples. This paper presents a detector of bunches of one fruit, grape, based on a deep convolutional neural network trained to detect vine bunches directly on the field. Experimental results show a 91% mean Average Precision.
Open AccessIn-Field Automatic Detection of Grape Bunches under a Totally Uncontrolled Environment
An early estimation of the exact number of fruits, flowers, and trees helps farmers to make better decisions on cultivation practices, plant disease prevention, and the size of harvest labor force. The current practice of yield estimation based on manual counting of fruits or flowers by workers is a time consuming and expensive process and it is not feasible for large fields. Automatic yield estimation based on robotic agriculture provides a viable solution in this regard. In a typical image classification process, the task is not only to specify the presence or absence of a given object on a specific location, while counting how many objects are present in the scene. The success of these tasks largely depends on the availability of a large amount of training samples. This paper presents a detector of bunches of one fruit, grape, based on a deep convolutional neural network trained to detect vine bunches directly on the field. Experimental results show a 91% mean Average Precision.