Frank Schäfer

A new approach for estimating the system response time (SRT) is presented and demonstrated through the analysis of the effect of target latitude on SRT, both with and without inter-satellite links (ISL). The access time intervals for each satellite to ground stations, targets, and between pairs of satellites are computed. The SRT for a target is calculated using a proposed algorithm that includes an adapted Dijkstra algorithm on a time-varying link graph for the ISLs. For the geospatial analysis, the average, minimum, and maximum SRTs of the targets of all SRTs were introduced as performance metrics. Combined with a visualization on a world map, this method allows us to quickly grasp the strengths and weaknesses of the constellation with regards to SRT. When plotted as a function of latitude [− 90°, 90°], the SRT for constellations with and without ISL in mid and high-inclination orbits peaks at the equator and drops towards the Earth’s poles, influenced by the satellite constellation and ground station network design. ISLs smoothen the SRT curve and reduce the effect of the latitude, thereby enhancing data acquisition speed by minimizing SRT variation over time and across longitudes.

Small satellites like CubeSats and Nanosatellites have been constantly evolving over the last decades. Due to the minimization of development costs and time by using commercial off the shelf (COTS) components for their construction, small satellites have become a cost-efficient alternative to conventional satellites for many applications. Since the COTS components are not designed to withstand harsh environmental conditions like extreme temperature ranges and high radiation levels, they provide only a limited lifespan and a reduced reliability in space. To overcome this issue an advanced data processing unit (DPU) is currently being developed at the Fraunhofer EMI. It will provide strong and reliable onboard processing capabilities for the upcoming ERNST nanosatellite mission. The heterogenous multiprocessor system on a chip (SoC) on which the DPU is based on allows the implementation of different concepts that improve the system’s reliability on a single COTS-SoC. The effectiveness of these protective measures is currently tested by extensive Hardware-in-the-Loop (HiL) tests. Once the HiL testing is completed, radiation tests and two in orbit demonstration will be carried out so the outcome of HiL tests can be validated.