Cristina Medina-Bailon

The progress of the microelectronics industry is primarily due to the scaling of MOSFETs, the fundamental device in modern integrated circuits. Throughout this evolution, TCAD tools have played a vital role in elucidating the operating principles and in exploring its design space. The increase in the overall complexity of the device architecture and material combinations necessitates the use of advanced physics-based models. This results in increased computational resource requirements. In this work, we demonstrate a machine learning-enhanced simulation framework for advanced MOSFET architectures. We develop a gradient-aware training dataset construction scheme that reduces the training data requirements by up to 72% and the training time by up to 78.4% for electrostatic potential while maintaining high accuracy. To improve the DNN training at intermediate gate biases, we employ synthetic data based on MOSFET operating principles for electron concentration. We benchmark the DNN-based TCAD solver by comparing electron concentration and electrostatic potential spatial profiles with the conventional physics-based solver. The predicted transfer characteristics show excellent agreement with experimental measurements of two advanced MOSFETs. The proposed framework computes complete transfer characteristics, including spatially resolved electron concentration and electrostatic potential profiles, in just 0.35 s, enabling rapid design-space exploration.

We investigate the physical mechanism linking subthreshold swing (SS) degradation and SS saturation in cryogenic n-type gate-all-around MOSFETs. While previous studies attributed SS saturation to source-to-drain direct tunneling (SDDT), we clarify that SDDT alone does not necessarily cause saturation. To the best of our knowledge, this study is the first to systematically establish that SS degradation arises when the drain current is dominated by Fermi-level-pinned tunneling that is insensitive to gate modulation in the deep subthreshold regime, and that SS saturation occurs only when this degradation overlaps with the current range relevant to device operation. Moreover, our results indicate that SS degradation can, under certain conditions, not only lead to saturation but also cause a direct increase in SS, making its impact even more critical for aggressively scaled devices. Using quantum transport NEGF simulations with a GAA MOSFET structure, we accurately analyze tunneling effects and suggest that the underlying physical mechanism is not limited to this specific device geometry. These findings provide a unified understanding of SS degradation and saturation for cryogenic CMOS technologies.

The capacitance of the gate oxide is a crucial parameter to model the performance of MOSFETs. The traditional expression used to compute it stems from the parallel-plate capacitor formula. While its use is appropriate for planar devices, it has been naturally extended to 3-D devices such as those based on nanosheets even if the geometry is quite different. In this work, we compute numerically the gate oxide capacitance of nanosheet transistors and, observing a nonnegligible discrepancy with the planar model, we propose a simple model that better reproduces the computed capacitance. Then, we investigate the definition of equivalent oxide thickness (EOT), showing that it cannot be strictly used for nonplanar devices: however, our improved model allows us to obtain a useful expression valid for the most common cases. Finally, we generalize the capacitance model to nanosheets with rounded corners.

Spatial confinement is important in advanced More Moore devices, such as nanowire transistors (NWTs), where the basic charge transport properties must be revised beyond the bulk crystal assumptions. This work presents a comprehensive and general overview of the electron mobility in aggressively-scaled Si NWTs in order to demonstrate the effect of quantum confinement on this topic, establishing its dependence on numerous physical factors (shape, diameter, and orientation). The mobility evaluation makes use of a unique simulation framework and innovative multi-subband calculations of the scattering rates. We show that (1) the effect of surface roughness scattering is more pronounced at higher sheet densities, (2) ionized impurity scattering seriously degrades the mobility in highly-doped NWTs, and (3) the cross-section shape affects directly the subband parameters and the mobility, with the elliptical NWTs giving the best performance for the same cross-sectional area.

As an attempt to improve the description of the tunneling current that arises in ultrascaled nanoelectronic devices when charge carriers succeed in traversing the potential barrier between source and drain, an alternative and more accurate non-local formulation of the tunneling probability was suggested. This improvement of the probability computation might result of particular interest in the context of Monte Carlo simulations where the utilization of the conventional Wentzel-Kramers-Brillouin (WKB) approximation tends to overestimate the number of particles experiencing this type of direct tunneling. However, in light of the reformulated expression for the tunneling probability, it becomes of paramount importance to assess the type of potentials for which it behaves adequately. We demonstrate that, for ensuring boundedness, the top of the potential barrier cannot feature a plateau, but rather has to behave quadratically as one approaches its maximum. Moreover, we show that monotonicity of the reformulated tunneling probability is not guaranteed by boundedness and requires an additional constraint regarding the derivative of the prefactor that modifies the traditional WKB tunneling probability.

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