Giuseppe Lipari

Parametric Worst-Case Execution Time (WCET) is a static analysis that computes a WCET formula that depends on various parameters. The formula can be used off-line for fast parameter space exploration, and on-line for adaptive scheduling. In this work, we propose a technique that, by static analysis of binary code, automatically produces a formula that represents the WCET of a procedure as a function of the procedure arguments. The formula captures how the control-flow, and thus the WCET, depends on the argument values due to arguments appearing in branch conditions (loop conditions or if-then-else conditions). We use the TACLeBench benchmark programs to illustrate the impact of procedure arguments on the WCET. Our tool generates C code with bounded WCET that can be embedded in the analysed program to evaluate the formula on-line. We show that, for some programs, the potential gain is significantly larger than the cost of evaluating the formula, thus opening the possibility of adaptive scheduling.

In this paper, we address the problem of analyzing the behavior of a set of real-time tasks on a Network-on-chip-based (NoC) architecture. Our approach is to transform the allocation of tasks and communications within a NoC into a classical real-time allocation problem. It provides an extension of classical bin-packing heuristics to allocate a set of real-time applications modeled using a directed acyclic graphs (DAGs) to a set of processors interconnected through a NoC.The paper describes the schedulability analysis, including allocation and communication. It provides also a comparative study of different allocation and communication algorithms and presents accordingly a set of promising research insights.

Recent commercial hardware platforms for embedded real-time systems feature heterogeneous processing units and computing accelerators on the same System-on-Chip. When designing complex real-time applications for such architectures, the designer is exposed to a number of difficult choices, like deciding on which compute engine to execute a certain task, or what degree of parallelism to adopt for a given function. To help the designer exploring the wide space of design choices and tune the scheduling parameters, we propose a novel real-time application model, called HPC-DAG (Heterogeneous Parallel Condition Directed Acyclic Graph Model), specifically conceived for heterogeneous platforms. An HPC-DAG allows the system designer to specify alternative implementations of a software component for different processing engines, as well as conditional branches to model if-then-else statements. We also propose a schedulability analysis for the HPC-DAG model and a set of heuristic allocation algorithms aimed at improving schedulability for latency sensitive applications. Our analysis takes into account the cost of preempting a task, which can be non-negligible on certain processors. We show the use of our approach on a realistic case study, and we demonstrate its effectiveness by comparing it with state-of-the-art algorithms previously proposed in literature.

Many task models have been proposed to express and analyze the behavior of real-time applications at different levels of precision. Most of them target sequential applications with no support for parallelism. The digraph task model is one of the most general ones, as it allows modeling arbitrary directed graphs (digraphs) for sequential job releases. In this paper, we extend the digraph task model to support intra-task parallelism. For the proposed parallel multi-mode digraph model, we derive sufficient schedulability tests and a dichotomic search to improve the test pessimism for a set of $n$n tasks onto a heterogeneous single-ISA multi-core platform. To reduce the computational complexity of the schedulability test, we also propose heuristics for (i) partitioning parallel digraph tasks onto the heterogeneous cores, and (ii) assigning core operating frequencies to reduce the overall energy consumption, while meeting real-time constraints. The effectiveness of the proposed approach is validated with an exhaustive set of simulations.

Parametric Worst-case execution time (WCET) analysis of a sequential program produces a formula that represents the worst-case execution time of the program, where parameters of the formula are user-defined parameters of the program (as loop bounds, values of inputs, or internal variables, etc). In this article we propose a novel methodology to compute the parametric WCET of a program. Unlike other algorithms in the literature, our method is not based on Integer Linear Programming (ILP). Instead, we follow an approach based on the notion of symbolic computation of WCET formulae. After explaining our methodology and proving its correctness, we present a set of experiments to compare our method against the state of the art. We show that our approach dominates other parametric analyses and produces results that are very close to those produced by non-parametric ILP-based approaches, while keeping very good computing time.

Energy consumption is the result of interactions between hardware, software, users, and the application environment. Optimization of energy consumption has become crucial, energy metric is considered a critical metric, so it is important knowing how to measure and understand how energy is consumed on mobile devices. Accurate knowledge will allow us to propose different solutions to reduce energy consumption in order to improve the user experience. In this paper we propose an experimental methodology to build a model of the energy consumption of an application. We show in this paper how to build a simple predictive model of the energy consumption of an unconnected application based on precise measurements.