Wenxi Yao

To address circulating current and output current harmonic challenges in parallel three-level T-type inverters, this study proposes a cost-effective solution utilizing positively coupled inductors (PCIs) with synchronized carriers. The common-mode equivalent inductor of PCIs enhances filtering of the output current harmonics with smaller inductor sizes, reducing cost compared to uncoupled inductors. The differential-mode equivalent inductor, in conjunction with synchronized carriers, effectively suppresses the high-frequency circulating current (HFCC) compared to interleaved carriers with negatively coupled inductors. The control strategies for output current regulation, low-frequency circulating current suppression, and neutral point voltage balancing are designed based on the decoupled mathematical models. Besides, the parameter design processes of PCIs and controllers are provided, and the impact of parameter inconsistency on HFCC and system stability is analyzed. Simulations and experiments validate that the proposed solution achieves superior performance in terms of circulating current suppression, low harmonic distortion, neutral point voltage balancing, and dynamic response.

High-power converters and/or high-speed motor drives often operate at low-carrier ratios, particularly at higher fundamental frequencies (and consequential higher modulation indices), because of device switching limitations. For such applications, advanced modulation strategies are required to minimize current quality issues, together with complex corrections to manage a (usually) nonlinear progression into the overmodulation and six-step regions so that converter capacity and/or motor operating speeds can be maximized. To minimize harmonics, these strategies are typically synchronous with the target fundamental frequency, which complicates their use in closed loop systems where a constant calculation frequency is preferable for optimum controller performance and stability. This article addresses this issue, by combining concepts of synchronous optimal pulsewidth modulation (SOPWM) and magnetic flux synthesis using space vector pulsewidth modulation (SVPWM), to create a fixed calculation frequency three-segment vector pulsewidth modulation strategy (TSVPWM). Similar to SOPWM, TSVPWM generates a “corner hexagonal” magnetic flux linkage that achieves a comparable harmonic performance to SOPWM at high modulation indices. TSVPWM maintains a linear gain across the entire modulation range with a smooth transition into six-step operation, and can be easily integrated with high-performance motor control strategies because of its constant calculation frequency. Its performance has been validated using a high-speed motor at 380 V and 12 000 r/min.

Due to switching loss limitations, low carrier ratio operating conditions are common for medium- or high-voltage, high-power converters. In grid-connected applications, commonly used modulation techniques such as Sinusoidal Pulse Width Modulation (SPWM) and Space Vector Pulse Width Modulation (SVPWM) often fail to meet the grid requirements for current harmonic distortion under low carrier ratios. The adoption of multilevel techniques and Discontinuous Pulse Width Modulation (DPWM) can significantly reduce switching losses and improve the carrier ratio. However, conventional modulation strategies based on fixed carriers tend to generate substantial low-frequency harmonics at low carrier ratios, complicating the design of grid-connected filters. Selected Harmonic Elimination PWM (SHEPWM) can eliminate low-frequency harmonics, which can facilitate higher-order filters to meet grid harmonic requirements. However, its limited dynamic response hinders its widespread application. This paper presents a modified DPWM strategy based on variable triangular carriers (VC-DPWMA), implemented on a 3-level inverter. The proposed method achieves harmonic performance comparable to SHEPWM at low carrier ratios while overcoming the drawbacks of slow dynamic response. A low-power hardware platform is used to realize the proposed approach. Both simulation and experimental results validate the theoretical analysis and demonstrate the feasibility of the proposed method.

Digital control based on multisampling and multiupdating (MSMU) is a potential way to enhance the performance of grid-connected converters (GCCs). But the traditional model of MSMU pulse width modulation (PWM) can’t be used to predict high-frequency instability caused by perturbation sidebands. Multisampled GCCs’ high-frequency response is still unknown and needs to be further explored. In this study, as for three-phase multisampled GCCs, a multifrequency model of MSMU PWM is built and verified, which considers perturbation sideband harmonics. Then, the output admittance model of multisampled GCCs is derived and can accurately describe the high-frequency admittance characteristics. High-frequency stability and the factors related to the impact of sideband coupling on stability are analyzed in detail. Compared with traditional one, the proposed model has higher accuracy in high-frequency band, which can predict high-frequency stability accurately. Finally, experimental results verify the effectiveness of the theoretical analysis presented above.

To deal with frequency deviation, the frequency-adaptive feedback (FAF) of phase-locked loop based on dual second-order generalized integrator (DSOGI-PLL) is necessary. However, in previous works, the FAF is usually ignored in small-signal impedance model of grid-connected inverter (GCI), which leads to inaccurate modeling and stability analysis. Therefore, considering the FAF, the models of DSOGI-PLL and GCI impedance are derived and verified in this article. It is found that the FAF introduces the positive feedback effect in PLL control loop and a decrease of low-frequency GCI impedance. It easily leads to instability in weak grids according to the impact of DSOGI-PLL parameters on stability. Then, a FAF approach based on low-pass filter (LPF) is presented to enhance stability. A parameter design guideline is also provided here. Finally, the experimental results demonstrate the effectiveness of the built model and stability analysis. In addition, based on the built model, the low-frequency passivity enhancement strategies for GCI under DSOGI-PLL with FAF can be further explored.

Interleaving technology in paralleled three-phase voltage-source converters (VSCs) can reduce the dc-link ripple current to improve the power density and lifetime of the dc-link capacitors. However, the carrier-based phase-shifting method commonly used for interleaving cannot achieve the minimum dc-link capacitor current stress, and it is difficult to determine the optimal interleaving angle in real-time control under different operation conditions. The article proposes a modulation strategy to minimize the dc-link capacitor current stress for paralleled VSCs with interleaving under a three-phase balanced load. Unlike the frequency domain analysis method, the effect of interleaving on reducing dc-link ripple current is explored by vector analysis in the time domain. Then, the optimal vector action times are determined based on solving the mathematical model of the linear programming optimization problem, as three degrees of freedom in vector time allocation that can be used for the dc-link current stress optimization exist in interleaved VSCs. The vector sequence suitable for the proposed modulation strategy is selected while considering the circulating current. Finally, analysis and experiments verify that the proposed strategy can reduce dc-link capacitor current stress by about 60% under wide operation conditions compared with the conventional space vector modulation.