Yuxiao Zhang

Data transaction promotes data circulation and mitigates the issues of Data Island. However, unlike traditional physical goods, data can be easily copied. This feature always induces leakage after selling the right of use in the transaction, resulting in the loss of users’ interest. In fact, it is difficult to restrain when buyers make backups and leak after purchasing the complete data. Therefore, it’s necessary to design corresponding schemes to ensure the data security in the transaction process, find the data after the buyer leaked and identify the malicious leaker. In this paper, we propose a data transaction architecture with leakage tracing by blockchain and digital fingerprint. In our architecture, buyers interact with sellers who pass the screening through the smart contracts. The digital fingerprint is utilized to avoid the malicious behavior of sellers and track leaked data by buyers. Then we provide an improvement plan to optimize the scheme of leakage tracing in data transactions by combining reporting and deposit mechanisms. In addition, we develop a Decentralized Application (DApp) to build the model for data transaction and leakage tracing. Experiments on the DApp demonstrate the effectiveness and feasibility of our proposed architecture.

Cooperative driving at signal-free intersections, which aims to improve driving safety and efficiency for connected and automated vehicles, has attracted increasing interest in recent years. However, existing cooperative driving strategies either suffer from computational complexity or cannot guarantee global optimality. To fill this research gap, this paper proposes an optimal and computationally efficient cooperative driving strategy with the polynomial-time complexity. By modeling the conflict relations among the vehicles, the solution space of the cooperative driving problem is completely represented by a newly designed small-size state space. Then, based on dynamic programming, the globally optimal solution can be searched inside the state space efficiently. It is proved that the proposed strategy can reduce the time complexity of computation from exponential to a small-degree polynomial. Simulation results further demonstrate that the proposed strategy can obtain the globally optimal solution within a limited computation time under various traffic demand settings.

Series and parallel resonance tend to occur and cause harmonic distortion when the distribution system contains a shunt power capacitor to compensate inductive load and dynamic capacitor (D‐CAP) to suppress harmonics. This study focuses on the series and parallel resonance active damping of three‐phase buck‐type D‐CAP, so as to achieve better power quality control. Two virtual resistor damping methods for series resonance, D‐CAP power capacitor voltage or D‐CAP front‐end buffer inductor current feedback, are introduced and compared. Then, parallel resonance is damped by generating certain harmonic currents in the phase with the selective harmonic voltage at the point of common coupling (PCC), equivalent to controlling the D‐CAP as a virtual harmonic resistor. In addition, the power balance of D‐CAP is interpreted to ensure no additional energy control loop is needed for the active damping. To further improve the parallel resonance damping, the self‐adjusted damping gain is proposed by the closed‐loop regulation of harmonics in PCC voltage. Finally, coordinated control between reactive and multiple harmonic currents is introduced for the whole combined control to avoid over‐modulation. A wide variety of experimental results from a 33 kVar/220 V laboratory prototype are provided to demonstrate the validity of the combined control.

In this paper, 100kHz sampling and switching frequency shunt active power filter (SAPF), which is based on a dual-core DSP TMS320F28377D, is designed for the potential market of high-frequency harmonic suppression in more electric aircraft (MEA) or high-speed train (HST). By utilizing the multithreading and multiprocessing method, the different computation segments, such as analog-to-digital conversion, recursive discrete Fourier transform (RDFT), inner-loop current and outer-loop voltage control, can be rearranged as several parallel operation groups. Compared to the traditional single pipeline structure of the mostly 10~20kHz switching frequency commercial SAPF, this parallel execution speeds up the signal processing so that the highly increased sampling frequency makes the current control loop reaches wider bandwidth even with simple PI regulator. Meanwhile, for wideband harmonic suppression, a multiresolution RDFT strategy is proposed to extend the range of the selected harmonic without sacrificing its extraction accuracy. After raising the sampling frequency to 100kHz, the proposed SAPF with much easier current controller could suppress wider frequency harmonics than other 10~20kHz SAPF. A 10kVA prototype with CREE SiC power module CCS050M12CM2 is set up to verify its effectiveness. The result complies with the IEEE standard 519-2014.

By adding Buck-type AC/AC converter to conventional power capacitor, dynamic capacitor (D-CAP) can be formed to compensate variable rather than fixed reactive power. However, some nonlinear distortion factors, namely grid harmonic voltage, voltage drop of switches and dead-time, would cause harmonics in its compensation current, meanwhile, its capacitance may interact with the grid inductance to cause series resonance. Both nonlinear distortion factors and series resonance would distort the waveform of its compensation current and make the grid current failed to meet the power quality standard IEEE Std.519. This paper focuses on the output current distortion of Buck-type D-CAP in reactive power compensation. For harmonic distortion, through establishing the equivalent circuit of Buck-type D-CAP, the generation of low-order harmonic current is investigated under three nonlinear factors. A current reshaping method to simultaneously diminish the harmonics caused by the three nonlinear distortion factors is thus adopted, which is a feedback control of output current harmonics. Then for series resonance, based on the block diagram of Buck-type D-CAP within the grid, transfer function from grid voltage to the output current is deduced and the corresponding Bode diagram is depicted. An active damping method is therefore suggested to shrink the low-order series resonance peak, by detecting power capacitor’s voltage for feedback control. Finally, a combined control, reactive current reshaping with series resonance damping is proposed in this paper for three-phase Buck-type D-CAP. A wide variety of experimental results from a 33kVar/220V laboratory prototype are provided to demonstrate the validity of the combined control.

In this paper, a unique 100kHz sampling and switching frequency shunt active power filter (SAPF), which is based on a dual-core DSP TMS320F28377D, is designed to achieve high control bandwidth for the potential market of wide frequency range harmonic suppression and resonance damping in future more electric aircraft (MEA) or high-speed railway power grid. By rearranging different computation segments, such as analog-to-digital conversion, recursive discrete Fourier transform (RDFT), inner-loop current and outer-loop voltage control, the traditional single pipeline code structure in DSP can be reformed as two parallel running groups. This multitasking strategy provides the proposed SAPF with huge advantages on higher frequency harmonic suppression compared to the mostly commercial SAPF with 10~20kHz switching frequency. Detailed parameter design of LCL filter, DC-side capacitor and deadtime are also presented. A 10kVA prototype utilizing CREE SiC power module CCS050M12CM2 is set up to verify the effectiveness of the proposed SAPF. The results show that the total harmonic distortion can be limited within 5%, which complies with the IEEE power quality standard 519-2014.

Dynamic capacitor (D‐CAP) could be designed to compensate reactive power and suppress harmonic currents simultaneously by means of regulating DC and harmonic terms in duty‐ratio modulation signal. However, the main constraint is that the amplitudes of DC and harmonic terms are always correlative, leading to the interaction between reactive and harmonic currents of D‐CAP. To minimise mutual effects between reactive and harmonic currents, this study presents coordinated control between reactive compensation and harmonic suppression for buck‐type D‐CAP. The major concern of coordinated algorithm is to pre‐estimate and select the DC and harmonic terms reasonably according to their inter‐constraint relationship. Thus, D‐CAP can optimise the generation of reactive and harmonic current references in different scenarios. Meanwhile, selective current control in multiple synchronous reference frames is employed to regulate reactive and harmonic current effectively. A series of experimental results are provided to verify the correctness of proposed coordinated control.

The modular multilevel converter (MMC) is attractive for medium‐ and high‐power applications because of its high modularity, availability and power quality. In this study, a quadruple sampling phase‐shifted‐carrier pulse‐width modulation (PSC‐PWM) strategy based on hierarchical distributed control architecture for MMC in medium‐voltage power distribution static synchronous compensator (DSTATCOM) application is presented. Compared to centralised control architecture, the multi‐digital signal processors master–slave hierarchical control architecture can enhance the scalability of MMC‐DSTATCOM and the sub‐module (SM) number can expand without limitation. To take advantage of the proposed hierarchical architecture, the multiple sampling PSC‐PWM technique is employed to improve the converter performance. The spectrum of the electromotive force of MMC with quadruple sampling is almost the same as that of natural sampling, which leads to fewer harmonics in reactive and harmonic current compensating. Besides, it also raises the sampling frequency so that the MMC‐DSTATCOM can compensate harmonic at the low SM switching frequency. The effectivenesses of the proposed architecture and modulation method are verified by experimental results obtained from a 60 V/2 kVA downscaled prototype.

This paper addresses the stability analysis of shunt active power filter (SAPF) with capacitive load for selective harmonic suppression and resonance damping. If the capacitive load current is measured as part of harmonic suppression current reference, the SAPF with conventional selective harmonic suppression would amplify the corresponding harmonic beyond resonance frequency. Previous studies could not clearly explain this harmonic amplification phenomenon without the selective harmonic extraction model in stability analysis. By viewing discrete Fourier transform (DFT) as cluster of band-pass filter (BPF), the modeling process is taken into consideration and is well simplified. The stability condition for suppressing and damping each selected harmonic can be easily estimated with the help of Nyquist stability criterion or root locus method in different SAPF control scenarios. To avoid the instability and compensate the harmonic current, a novel combined control strategy of SAPF is carried out to simultaneously suppress the harmonics whose frequencies are lower than the resonance frequency and mitigate the rest of harmonics by resonance damping method. Experiments have been performed to verify the effectiveness of the proposed strategy.