Elyas Zamiri

This paper presents the development and experimental validation of a custom Field-Programmable Gate Array (FPGA)-based hardware-in-the-loop (HIL) emulator for high-power induction motor drives. The proposed system enables real-time emulation of a variable-frequency drive consisting of a diode rectifier, a two-level voltage source inverter (VSI), and a 215 HP induction machine. The emulator is implemented on an NI PCIe-7857R FPGA platform using LabVIEW FPGA and fixed-point arithmetic optimised for Kintex-7 resources. A key contribution of this work is the achievement of a 100 ns real-time simulation time step for the converter and machine models, enabling accurate representation of fast switching dynamics while avoiding aliasing effects typically encountered in HIL systems. A multi-rate architecture is adopted to allocate appropriate sampling frequencies to different subsystems, improving computational efficiency and stability. Experimental results obtained from a closed-loop setup with an sbRIO-based controller demonstrate accurate emulation of inverter operation, induction machine dynamics, and controller interactions. The developed platform also enables detailed investigation of switching phenomena, such as voltage spikes, dead-time effects, and current ripple. Comparative validation with a Typhoon HIL 602+ platform confirms similar dynamic behaviour and harmonic performance, demonstrating that the proposed low-cost FPGA-based solution provides a flexible and high-fidelity alternative for real-time power electronics research and controller development.

Power quality is one of the most critical fields in the energy sector. The connection of electric vehicles to the electrical grid can cause a degradation of energy quality when charging or discharging the battery. Identifying sudden voltage drops, surges, and network interruptions is essential to avoid network failure. A multiple fault classification/monitoring system has been developed based on artificial neural networks and implemented in an FPGA. The system’s performance has been evaluated using a set of data obtained from MATLAB/Simulink 2024. Different dataset combinations are implemented, trained, validated, and tested on three multilayer perceptron (MLP) models of various configurations. The analysis shows that the MLP designed with 12-bit fixed-point data precision is the most efficient MLP implementation in classification accuracy, compared to 8, 12, 20, and 24-bit fixed-point data. The system achieved 99.95% classification accuracy across various fault conditions, demonstrating its capability for real-time deployment.

Recent advancements in FPGA technology have made these devices a cost-effective alternative for implementing Model Predictive Controllers (MPCs). This paper addresses the fast prototyping of FPGA-based Finite Control Set (FCS)-MPCs and the essential verification process preceding hardware-level testing. The methodology leverages MATLAB HDL Coder for automated HDL code generation. This approach offers a streamlined process and eliminates the need for expertise in hand-coded HDL, making it an ideal solution for power electronics engineers. The approach is exemplified using a three-phase active neutral point clamped converter. Beyond presenting the design approach, the paper introduces a systematic multi-stage verification process essential for the rapid prototyping of FCS-MPC controllers. This verification involves step-by-step simulations followed by experimental hardware-in-the-loop tests, ensuring the reliability of each stage for the smooth transition from pure simulation to FPGA hardware implementation of the controller. The proposed methodology not only simplifies the implementation and testing of the MPC algorithm within an FPGA but also facilitates the debugging process, a crucial aspect of the design phase.

Model Predictive Control (MPC) is widely adopted for power electronics converters due to its ability to optimize system performance under dynamic constraints. However, its FPGA implementation remains challenging due to the complexity of Hardware Description Language (HDL) programming. This paper addresses this challenge by introducing a straightforward methodology that simplifies FPGA implementation using MATLAB R2022b Simulink HDL Coder. It is shown that HDL Coder yields favorable synthesis outcomes, both in terms of area and time, compared to hand-coded HDL. Notably, the proposed method achieves a significantly reduced sampling step for the MPC algorithm—down to 32 ns—marking a substantial improvement over state-of-the-art implementations. The Integrated Logic Analyzer (ILA) IP available in the Vivado tool is used during the HIL testing phase to facilitate the real-time observation and analysis required for debugging and confirming the FPGA-implemented controller performance. Additionally, this paper discusses the advantages of utilizing HDL Coder for simplifying the FPGA programming process in power electronics applications and addresses the design challenges encountered using this methodology.

Finite Control Set Model Predictive Control emerges as a promising method for controlling power electronics inverters, outperforming traditional linear techniques. However, implementing Finite Control Set Model Predictive Control on conventional processors faces a significant computational burden due to its repetitive nature. This paper presents a novel approach that utilizes LabVIEW & Field Programmable Gate Arrays to address this computational bottleneck. By capitalizing on the inherent parallelism and suitability of Field Programmable Gate Arrays for discrete control problems, substantial computational advantages are achieved for Finite Control Set Model Predictive Control. The use of LabVIEW, a well-established platform in industrial and commercial solutions, ensures that this work is relevant not only academically but also for real-world industrial applications of FCS-MPC in power electronics and motor drives. This research successfully demonstrates the application of Finite Control Set Model Predictive Control for controlling the current of a motor-like load for a three-phase Voltage Source Inverter system in LabVIEW. To simplify the traditionally complex Field Programmable Gate Arrays programming process, user-friendly toolkits such as LabVIEW Control Design & Simulation, LabVIEW Real-Time, and LabVIEW FPGA Module are employed. This LabVIEW-based integration facilitates the execution of both concurrent and sequential Field Programmable Gate Arrays algorithms, leading to efficient Field Programmable Gate Arrays resource management and user-defined restrictions on maximum switching frequency, obviating the need for resource-intensive control methods for fast switches such as SiC and GaN IGBTs. The proposed controller is validated using an off-the-shelf computer turned into a real-time system but also on Field Programmable Gate Arrays for comparison purposes.

Model Predictive Control (MPC) has emerged as a promising alternative for controlling power converters, offering benefits such as flexibility, simplicity, and rapid control response, particularly when short-horizon algorithms are employed. This paper introduces a system using a short-horizon Finite Control Set MPC (FCS-MPC) strategy to specifically address the challenge of non-minimum phase behavior in boost converters. The non-minimum phase issue, which complicates the control process by introducing an initial inverse response, is effectively mitigated by the proposed method. A Proportional–Integral (PI) controller is integrated to dynamically adjust the reference current based on the output voltage error, thereby enhancing overall system stability and performance. Unlike conventional PI-MPC methods, where the PI controller has an influence on the system dynamics, the PI controller in this approach is solely used for tuning the reference current needed for the FCS-MPC controller. The PI controller addresses small deviations in output voltage, primarily due to model prediction inaccuracies, ensuring steady-state accuracy, while the FCS-MPC handles fast dynamic responses to adapt the controller’s behavior based on load conditions. This dual control strategy effectively balances the need for precise voltage regulation and rapid adaptation to varying load conditions. The proposed method’s effectiveness is validated through a multi-stage simulation test, demonstrating significant improvements in response time and stability compared to traditional control methods. Hardware-in-the-loop testing further confirms the system’s robustness and potential for real-time applications in power electronics.

This paper addresses aliasing oscillations encountered in hardware-in-the-loop (HIL) simulation caused by inaccurate duty cycle detection in high-frequency power electronic applications. Oversampling has been commonly used as a solution to detect switching events more accurately. Traditional oversampling methods use the extra information obtained by oversampling the inputs for further computations to enhance the precision of the simulation. However, these techniques increase the complexity of the model since they take into account several switch states during each simulation step. To mitigate these complexities, the integration oversampling method (IOM) was introduced as a recent alternative with minimum impact on the model complexity. IOM provides a modified switching pattern that effectively prevents aliasing oscillations while maintaining a single switch-state for each simulation step. It can be implemented as an independent block between the controller and the HIL model, so it keeps the HIL model unchanged. This study highlights the limitations detected in applying IOM to the models with complementary switches, including possible undesired short circuits. To overcome these limitations, a novel oversampling method called 4PIOM is presented. 4PIOM further enhances the IOM algorithm by reducing the simulation step and sampling period. The validity of the new method is demonstrated by comparison with previous proposals and also with the same model without any oversampling. Both experimental and MATLAB simulation results prove its superior performance in attenuating the aliasing oscillations and improving the quality of the simulation.

The ESA Control Toolbox is a new MATLAB toolbox that offers a quick, efficient, and practical alternative for the implementation of digital controllers into Field Programmable Gate Arrays (FPGAs) for space applications. This paper demonstrates the versatility and viability of the toolbox by showcasing its effectiveness in developing Hardware-In-the-Loop (HIL) models on FPGAs. While the straightforward way for implementing such models is by coding them in a Hardware Description Language (HDL), those languages are not trivial and render a cumbersome and time-consuming process. MATLAB Simulink HDL Coder blocks offer a more efficient and intuitive approach, though several issues arise from the fact that there is no static equivalence between blocks and VHDL code. In order to address these issues, the presented toolbox provides blocks that are linked to static VHDL code, enabling the design and synthesis of any kind of HIL model in FPGAs. This paper demonstrates the application of the toolbox in a case study for modeling a Three-Level Active Neutral-Point-Clamped (3L-ANPC) converter. The proposed toolbox results are compared with a MATLAB Simscape model incorporating both open and closed-loop controllers, yielding identical results and thus confirming the reliability and functionality of the ESA Control Toolbox as an alternative for creating FPGA-based HIL designs.

This paper addresses aliasing oscillations encountered in hardware-in-the-loop (HIL) simulation caused by inaccurate duty cycle detection in high-frequency power electronic applications. Oversampling has been commonly used as a solution to detect switching events more accurately. Traditional oversampling methods use the extra information obtained by oversampling the inputs for further computations to enhance the precision of the simulation. However, these techniques increase the complexity of the model since they take into account several switch states during each simulation step. To mitigate these complexities, the Integration Oversampling Method (IOM) is introduced as a recent alternative with minimum impact on the model complexity. IOM provides a modified switching pattern that effectively prevents aliasing oscillations while maintaining a single switch-state for each simulation step. It can be implemented as an independent block between the controller and the HIL model, so it keeps the HIL model unchanged. This study highlights the limitations detected in applying IOM to the models with complementary switches, including possible undesired short circuits. To overcome these limitations, a novel oversampling method called 4PIOM is presented. 4PIOM further enhances the IOM algorithm by reducing the simulation step and sampling period. The validity of the new method is demonstrated by comparison with previous proposals and also with the same model without any oversampling. Both experimental and MATLAB simulation results prove its superior performance in attenuating the aliasing oscillations and improving the quality of the simulation.