Jingfang Wang

To effectively suppress the input current harmonics of the 12-pulse rectifier, a novel multipulse rectifier with a single-switch controllable step-tripling interphase reactor (SSCST-IPR) at the dc side is proposed. The proposed SSCST-IPR consists of a single active switch, three auxiliary diodes, and an interphase reactor with a secondary winding. The coordinated modulation of the single active switch and the three auxiliary diodes modify the rectifier bridge’s output current into a three-level waveform. Based on the relationship between the ac- and dc-side currents, the number of input current steps increases from 12 to 36, and the total harmonic distortion is reduced from 11.8% to 2.3%. Since the proposed SSCST-IPR requires only one active switching device and its capacity is only 3.63% of the output power, the proposed scheme is characterized by a simple structure, small auxiliary circuit capacity, and low cost. An experimental prototype with an output power of 3.1 kW was constructed to verify the correctness and effectiveness of the theoretical analysis.

To enhance the harmonic suppression capability of the traditional 18-pulse rectifier, a delta-configured pulse-doubler circuit (DC-PDC) is proposed, and a new 36-pulse rectifier with DC-PDC is presented in this article. The DC-PDC consists of three dual-tapped converters and is installed on the dc side of the rectifier. The positive output terminals of three rectifier bridges serve as the input to the DC-PDC, and the output of the DC-PDC is connected to the load to supply power. The unique structure and connection method of the DC-PDC enable six auxiliary diodes to conduct cyclically, thereby increasing the output states of the rectifier bridges. This effect, in turn, increases the pulse number of the rectifier from 18 to 36, reducing the total harmonic distortion of the input current from 7.1% to 2.4% . The proposed scheme requires only a purely passive DC-PDC with a low KVA rating (7.35% P_d). It offers advantages, such as a simple circuit structure, easy implementation, high reliability, and low cost. A 1.5 kW prototype was built to verify the theoretical analysis.

In data center power systems, three-phase LLC resonant converters are widely adopted due to their advantages of electrical isolation and high power density. However, the conventional use of multiple discrete high-power transformers reduces both overall power density and efficiency. To address this issue, this paper proposes a novel three-phase magnetically integrated transformer design based on PQ cores. By optimizing the multi-layer winding structure, the proposed transformer ensures balanced current sharing among parallel windings under high-frequency conditions. Additionally, by sharing the side limbs between adjacent phases, the core volume and weight are further reduced. The feasibility of the proposed transformer is validated through magnetic circuit analysis, finite element simulation, and experimental testing. Compared with traditional magnetic integration methods, the proposed approach eliminates the need for custom magnetic cores, simplifying the manufacturing process. Furthermore, compared with the design using multiple discrete transformers, the proposed transformer achieves a 14.3% reduction in core volume and weight. To verify the performance of the proposed design, a two-stage 15 kW three-phase LLC resonant converter was built and tested.

This article proposes a new torque sharing function (TSF) method with an adaptive-speed controller to reduce torque ripple and improve the dynamic response of switched reluctance motor (SRM). In order to address system uncertainty caused by the nonlinear characteristics of the SRM, the adaptive-speed controller, based on the mechanical equations of SRM, is designed to effectively track the desired speed and generate the required total torque. By distributing the desired total torque during commutation according to the torque-current ratio (TCR), a new TSF is proposed to ensure that phase torque regulation aligns with the torque output capability of each phase to reduce the current peak and torque ripple. In order to further mitigate torque tracking errors caused by SRM nonlinearity, a compensation method is introduced, using the phase with a higher TCR for error compensation, improving torque control accuracy. Additionally, a novel hybrid chopping pulse width modulation (PWM) method, based on the TCR and asymmetric topology, is proposed to reduce switching losses and torque ripple. Experimental results from a three-phase 12/8 SRM prototype validate the effectiveness of the proposed method in reducing the current peak, minimizing torque ripple, and improving system efficiency.