Jiang Luo

Reconfigurable metamaterials have enabled significant progress toward tunable microwave devices, yet existing approaches are often hindered by limited mechanical reconfigurability and susceptibility to electromagnetic interference. Here, we introduce a type of metamaterial robot that harnesses bistable Kresling origami to achieve dynamic electromagnetic control. By integrating pneumatically driven folding architectures with digital light processing–printed SrTiO ₃ high‐permittivity ceramic patches, our design establishes a unified platform where mechanical deformation and microwave resonant behavior can be actively and synergistically regulated. The coupled extension‐twisting motion inherent to the Kresling geometry simultaneously tailors the axial height, in‐plane orientation, local propagation phase, and boundary conditions of the ceramic resonators, thereby modulating the excitation conditions of dielectric resonance responses across distinct frequency bands. Experimentally, transitioning a single origami unit from its folded state to its deployed state increases the number of resolvable reflection peaks from two to three, with a minimum reflectance reaching approximately −35.6 dB. Rotating the SrTiO ₃ patches further shifts the dual‐resonance center frequencies from 3.71–3.87 Hz and 16.72–17.26 GHz to 4.36–4.45 GHz and 16.31–16.72 GHz, respectively. Expanding this concept to a spatially heterogeneous origami array enables coupled control of both resonance peaks, yielding a minimum peak reflectance as low as −54.4 dB and a reflection modulation depth of 51.0 dB at 12 GHz.

A high-performance hybrid variable gain amplifier (HVGA) for K-band phased-array applications is presented in a 55 nm CMOS process. The proposed HVGA adopts a role-partitioned triple-stacked current-steering amplifier (TS-CSA)– $\pi $ PA architecture, where a $\pi $ -type passive attenuator ( $\pi $ PA) provides coarse attenuation while a TS-CSA performs fine gain stepping. Within the TS-CSA, a triple-stack core and a binary-weighted current-steering array suppress parasitic coupling and render temperature-induced variations largely common-mode across gain states, while a complementary capacitor co-switching scheme stabilizes the critical-node capacitance and suppresses state-dependent phase shifts. This hybrid topology improves the linearity–efficiency tradeoff and ensures wide-temperature consistency without temperature-compensation circuitry. The fabricated prototype occupies a compact 0.17-mm² core area and provides a 15.5-dB gain control range (GCR) with 0.5-dB resolution over 17–22GHz. Measurements from $- 55~^{\circ }$ C to $125~^{\circ }$ C confirm stable gain-state consistency, with root-mean-square amplitude and phase errors below 0.35 dB and 3.5°, and temperature-induced variations within 0.22 dB and 0.8°, respectively. The minimum peak gain over 17–22 GHz at $125~^{\circ }$ C remains above −0.71 dB. Even at $125~^{\circ }$ C, the measured IP ${}_{\mathrm {1 dB}}$ remains better than −1.5 dBm with only 8.5 mW power consumption. These results demonstrate a compact, low-power, and thermally robust K-band gain-control solution for phased-array applications.

This paper presents a 90–100 GHz wideband digital phase shifter with a fine resolution of 5.625°, implemented in a 0.13 μm SiGe BiCMOS process. A switch-type architecture with six cascaded units, including a novel 180° cell based on a broadband coupler, enables full 0–360° phase coverage while improving phase accuracy, bandwidth, and process robustness. Post-layout simulations demonstrate an insertion loss below 15.5 dB, an RMS phase error under 2.3°, and an RMS amplitude error better than 0.9 dB across the 90–100 GHz band. The total chip area, including test pads, is 0.39 mm², making the design compact and well suited for high-density phased-array applications.

Reconfigurable Intelligent Surfaces (RISs) are a key enabler for next-generation wireless communications. However, the power consumption associated with tuning components remains a significant challenge. This letter presents a novel single-pole single-throw (SPST) switch designed and implemented using a 55 nm bulk CMOS process, achieving high energy efficiency with a low driving voltage. The design features a decoupled control port and RF path port, greatly simplifying the feeding network and enhancing integration flexibility. For verification, a 12.5 GHz RIS with 144 units prototype incorporating the proposed SPST switch was fabricated and measured. Experimental results demonstrate a wide-angle scanning range of ±50°, with a maximum array power consumption of only 0.44 mW and per-element power consumption as low as 3 μW—at least three orders of magnitude lower than traditional PIN-based RISs. This achievement sets a new benchmark for energy efficiency in RIS hardware, providing a cost-effective and scalable solution to enable large-scale deployment in future wireless communication systems.

This brief presents an efficient adaptive analog temperature compensation technique that stabilizes the amplitude and phase performance of an RF attenuator over an ultra-wide temperature range without compromising its other metrics. The approach utilizes an adaptive analog temperature-dependent voltage source (AATVS) to supply the binary digital control array, which indirectly biases the gate terminals of MOSFET switches in the attenuation unit. This method effectively mitigates thermal variations in on-resistance and intrinsic capacitance. To validate the technique, a 5-bit digital step attenuator (DSA) was designed and fabricated using a 0.13μ m SiGe BiCMOS process. The DSA exhibited excellent consistency in root-mean-square (RMS) amplitude and phase errors across.55 ° C to 125 ° C, achieving an RMS attenuation error below 0.24 dB, an RMS phase error under 2.3°, and an insertion loss (IL) better than 4.9 dB over 10–15 GHz. To the best of the authors’ knowledge, this work is the first to implement an AATVS-based compensation mechanism in a 5-bit DSA, ensuring stable amplitude and phase accuracy under extreme thermal variations.

A high-linearity down mixer with outstanding robust temperature tolerance for V-band applications is proposed in this paper. The mixer’s temperature

This paper presents a compact V-band low-noise amplifier (LNA) featuring temperature compensation, implemented in a 130 nm SiGe BiCMOS process. A negative temperature coefficient bias circuit generates an adaptive current for temperature compensation, enhancing the LNA’s temperature robustness. A T-type inductive network is employed to establish two dominant poles at different frequencies, significantly broadening the amplifier’s bandwidth. Over the wide temperature range of −55 °C to 85 °C, the LNA prototype exhibits a gain variation of less than 1.5 dB at test frequencies from 40 GHz to 65 GHz, corresponding to a temperature coefficient of 0.01 dB/°C. At −55 °C, 25 °C, and 85 °C, the measured peak gains are 25.5 dB, 25 dB, and 24.4 dB, respectively, with minimum noise figures (NF) of 3.0 dB, 3.5 dB, and 4.2 dB, and DC power consumptions of 22.3 mW, 27.6 mW, and 34.4 mW. Moreover, the total silicon area of the LNA chip is 0.37 mm², including all test pads, while the core area is only 0.09 mm².

Reconfigurable intelligent surfaces (RISs) are of potential use in 5G/6G wireless communications due to their tunable electromagnetic (EM) parameters for flexible beam manipulations. Two important parameters for RIS design are the reflection coefficient of the RIS element and the scattering pattern of the RIS. To realize rapid design of RISs, we propose a zero-pole-based multiport model to calculate the reflection coefficients and scattering patterns of RISs in this work. Specifically, the developed model establishes an accurate mapping relation between the element reflection coefficient and the loads on multiple internal ports by using the multiport S-parameter matrix. Additionally, the vector fitting method is employed to reduce the time cost of data acquisition for multiport S-parameters, in which a hybrid sampling scheme is employed to accelerate computation speed while keeping high accuracy. Using this model, we further develop an efficient far-field pattern prediction and synthesis algorithm for large-scale RIS design based on the antenna radiation superposition principle. The feasibility of the proposed model is demonstrated by an example of 3-bit RIS design, where the simulation results agree well with the measurement.