Atsushi Hiraiwa
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Atsushi Hiraiwa has a total of 116 co-authors. Here are the top co-authors by number of shared publications:
- Hiroshi Kawarada
Waseda University
31 shared publications Akio Nishida
10 shared publicationsKiyotaka Horikawa
Faculty of Science and Engineering, Waseda University, Tokyo, Japan
6 shared publications- Kiyotaka Horikawa
Faculty of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan
6 shared publications - Satoshi Okubo
Faculty of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan
5 shared publications Akio Shima
Central Research Laboratory, Hitachi Ltd., Tokyo, Japan
3 shared publications
Latest Publications
- Open Access
- 6 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 47 (3) , 574-577
Heavily Boron-Doped Source/Drain Layers for Low Contact Resistance and Subthreshold Swing in (001) C–H Diamond MOSFETs
The effect of a heavily boron-doped (p+) source/drain (S/D) layers ([B]: 2–8 × 1020 cm-3) are examined compared with conventional Au/diamond S/D contacts without p+ on the same hydrogen-terminated (C-H) diamond metal-oxide-semiconductor field-effect transistors (MOSFETs). The following points such as contact resistance (Rc), subthreshold swing (SS), on-resistance (Ron) and threshold voltage (Vth) are comparatively investigated between with/without p+ layers. The selective epitaxial growth of p+ S/D regions in (001) enhances the contact performance with the C-H diamond channel. It reduces the Rc between the metal S/D contacts and C-H diamond from 5.8 to 1.4 Ω·mm, which is the lowest reported for (001) diamond MOSFETs. For MOSFETs with a p+ layer and source-drain length of 2 μm, the SS is ~560 mV/dec, the on-resistance (Ron) is 0.78 mΩ·cm2, and the threshold voltage (Vth) is 3.4 V. In contrast, without the p+ layer, the SS is ~1600 mV/dec, the Ron is 1.44 mΩ·cm2, and the Vth is 13.7 V. Overall, the p+ layer is beneficial for the development of high-performance diamond MOSFETs using the (001) surface.
- 6 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 47 (3) , 574-577
Open AccessHeavily Boron-Doped Source/Drain Layers for Low Contact Resistance and Subthreshold Swing in (001) C–H Diamond MOSFETs
The effect of a heavily boron-doped (p+) source/drain (S/D) layers ([B]: 2–8 × 1020 cm-3) are examined compared with conventional Au/diamond S/D contacts without p+ on the same hydrogen-terminated (C-H) diamond metal-oxide-semiconductor field-effect transistors (MOSFETs). The following points such as contact resistance (Rc), subthreshold swing (SS), on-resistance (Ron) and threshold voltage (Vth) are comparatively investigated between with/without p+ layers. The selective epitaxial growth of p+ S/D regions in (001) enhances the contact performance with the C-H diamond channel. It reduces the Rc between the metal S/D contacts and C-H diamond from 5.8 to 1.4 Ω·mm, which is the lowest reported for (001) diamond MOSFETs. For MOSFETs with a p+ layer and source-drain length of 2 μm, the SS is ~560 mV/dec, the on-resistance (Ron) is 0.78 mΩ·cm2, and the threshold voltage (Vth) is 3.4 V. In contrast, without the p+ layer, the SS is ~1600 mV/dec, the Ron is 1.44 mΩ·cm2, and the Vth is 13.7 V. Overall, the p+ layer is beneficial for the development of high-performance diamond MOSFETs using the (001) surface.
- 8 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 72 (10) , 5483-5489
Effects of Regrown Layer Thickness and Nitrogen Concentration on Current Rise at Low Drain Voltage in Vertical Diamond MOSFET
Diamond is a promising material for power devices due to its excellent physical properties, and vertical p-channel field effect transistors (FETs) are important for realizing next-generation complementary inverters. In this study, we fabricated a (001) vertical diamond MOSFET using a 2-D hole gas (2DHG) induced by hydrogen-terminated diamond surfaces. The device incorporated a trench structure with a$1.5~\boldsymbol {\mu } $ m over-etch depth into the boron-doped diamond (p+) substrate. However, a suppressed drain current rise was observed in the low-voltage region (−4 V$\boldsymbol {\le } {V}_{\text {DS}}~\boldsymbol {\le }0$ V). To investigate the cause, we measured trench-type lateral devices in which the current does not pass through the regrown layer and increases rapidly in the low-voltage region. These results indicate that the regrown layer at the bottom of the trench is the dominant factor suppressing the drain current rise. Device simulations were performed with a fixed trench over-etch depth of$1.5~\boldsymbol {\mu } $ m while varying the thickness and nitrogen concentration of the regrown layer. The results showed that increasing either parameter raises the potential barrier for holes to penetrate the regrown layer, thereby suppressing the current rise. Reducing the nitrogen concentration and thinning the regrown layer improved the current rise. These findings offer valuable insights into improving the performance of vertical diamond FETs and support their application in future complementary power inverters.- 8 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 72 (10) , 5483-5489
Effects of Regrown Layer Thickness and Nitrogen Concentration on Current Rise at Low Drain Voltage in Vertical Diamond MOSFET
Diamond is a promising material for power devices due to its excellent physical properties, and vertical p-channel field effect transistors (FETs) are important for realizing next-generation complementary inverters. In this study, we fabricated a (001) vertical diamond MOSFET using a 2-D hole gas (2DHG) induced by hydrogen-terminated diamond surfaces. The device incorporated a trench structure with a$1.5~\boldsymbol {\mu } $ m over-etch depth into the boron-doped diamond (p+) substrate. However, a suppressed drain current rise was observed in the low-voltage region (−4 V$\boldsymbol {\le } {V}_{\text {DS}}~\boldsymbol {\le }0$ V). To investigate the cause, we measured trench-type lateral devices in which the current does not pass through the regrown layer and increases rapidly in the low-voltage region. These results indicate that the regrown layer at the bottom of the trench is the dominant factor suppressing the drain current rise. Device simulations were performed with a fixed trench over-etch depth of$1.5~\boldsymbol {\mu } $ m while varying the thickness and nitrogen concentration of the regrown layer. The results showed that increasing either parameter raises the potential barrier for holes to penetrate the regrown layer, thereby suppressing the current rise. Reducing the nitrogen concentration and thinning the regrown layer improved the current rise. These findings offer valuable insights into improving the performance of vertical diamond FETs and support their application in future complementary power inverters.- 9 April 2025
- Published by American Vacuum Society in Journal of Vacuum Science & Technology B
- Vol. 43 (3)
Bias stability enhancement of metal/Al2O3/AlN/GaN capacitors by high-temperature plasma-enhanced atomic layer deposition of thin AlN interlayer
AlN films formed on (0001) GaN by a plasma-enhanced atomic layer deposition (PEALD) method at 200 and 450 °C without remote-plasma pretreatment (RPP) were crystalline as formed and epitaxially aligned with the GaN substrate. Even a 0.7-nm AlN film formed by high-temperature (HT, 450 °C) PEALD suppressed the bias instability of Al/Al2O3/AlN/GaN capacitors to a practically negligible level. By contrast, the bias instability improvement for low-temperature (LT, 200 °C) PEALD was quite limited. Although RPP was not conducted, the interface-state density of the HT-PEALD capacitors was reduced to 1.4 × 1011 cm−2 eV−1 for AlN thicknesses of ≤1.5 nm, supposedly owing to the RPP effect inherent in HT-PEALD. By contrast, LT-PEALD AlN films generated a considerable number of interface states. The HT-PEALD AlN interlayer possessed a polarization charge of −7.7 × 1013 cm−2 in units of electronic charge, comparable to a reported value of −8.7 × 1013 cm−2. The flatband-voltage shift of an Al/Al2O3/0.7-nm AlN/GaN capacitor caused by this polarization was −1.2 V. Similar to previous results, the net insulator charge, which comprised interface-state and GaN-polarization charges, was considerably smaller in magnitude than the GaN polarization charge, indicating the presence of highly positive interface-state charge compensating for the negative GaN polarization charge. A physical model for the interface-state charge was proposed. As the thin HT-PEALD AlN interlayer effectively suppressed the bias instability of Al2O3/AlN/GaN capacitors, retaining a good interface with the GaN substrate and causing a small flatband-voltage shift, as aforementioned, it will be a key to realizing high-performance and high-reliability GaN metal-insulator-semiconductor field-effect transistors.
- 9 April 2025
- Published by American Vacuum Society in Journal of Vacuum Science & Technology B
- Vol. 43 (3)
Bias stability enhancement of metal/Al2O3/AlN/GaN capacitors by high-temperature plasma-enhanced atomic layer deposition of thin AlN interlayer
AlN films formed on (0001) GaN by a plasma-enhanced atomic layer deposition (PEALD) method at 200 and 450 °C without remote-plasma pretreatment (RPP) were crystalline as formed and epitaxially aligned with the GaN substrate. Even a 0.7-nm AlN film formed by high-temperature (HT, 450 °C) PEALD suppressed the bias instability of Al/Al2O3/AlN/GaN capacitors to a practically negligible level. By contrast, the bias instability improvement for low-temperature (LT, 200 °C) PEALD was quite limited. Although RPP was not conducted, the interface-state density of the HT-PEALD capacitors was reduced to 1.4 × 1011 cm−2 eV−1 for AlN thicknesses of ≤1.5 nm, supposedly owing to the RPP effect inherent in HT-PEALD. By contrast, LT-PEALD AlN films generated a considerable number of interface states. The HT-PEALD AlN interlayer possessed a polarization charge of −7.7 × 1013 cm−2 in units of electronic charge, comparable to a reported value of −8.7 × 1013 cm−2. The flatband-voltage shift of an Al/Al2O3/0.7-nm AlN/GaN capacitor caused by this polarization was −1.2 V. Similar to previous results, the net insulator charge, which comprised interface-state and GaN-polarization charges, was considerably smaller in magnitude than the GaN polarization charge, indicating the presence of highly positive interface-state charge compensating for the negative GaN polarization charge. A physical model for the interface-state charge was proposed. As the thin HT-PEALD AlN interlayer effectively suppressed the bias instability of Al2O3/AlN/GaN capacitors, retaining a good interface with the GaN substrate and causing a small flatband-voltage shift, as aforementioned, it will be a key to realizing high-performance and high-reliability GaN metal-insulator-semiconductor field-effect transistors.
- Open Access
- 7 August 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 45 (9) , 1554-1557
Over 1 A Operation of Vertical-Type Diamond MOSFETs
Diamond is a promising material for p-channel power field-effect transistors (FETs) due to its remarkable physical properties. However, no diamond FETs with current characteristics exceeding 1 A have so far been reported. P-channel FETs capable of high-current operation are essential in order to realize complementary inverters with n-channel wide bandgap devices such as SiC or GaN. In this work, we designed and fabricated vertical-type diamond metal-oxide-semiconductor FETs (MOSFETs) with a trench structure, and a gate width (${W} _{\text {G}}\text {)}$ of 0.1 to 10 mm. For devices with${W} _{\text {G}} =10$ mm and a source-drain voltage (${V} _{\text {DS}}\text {)}$ of –20 V, the drain current reached 0.7 A. We obtained a maximum drain current of over 1.5 A with${V} _{\text {DS}} =$ –20 V by connecting two devices in parallel within a chip. The drain current density and specific on-resistance at a${V} _{\text {DS}}$ of –10 V were 85 mA/mm and$118~\Omega \cdot $ mm, respectively (${W} _{\text {G}} =2$ mm). The leakage current in the off state is at the lower limit of the measurement ($\sim 10^{-{11}}$ A) and the on/off ratio is over nine orders of magnitude.- 7 August 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 45 (9) , 1554-1557
Open AccessOver 1 A Operation of Vertical-Type Diamond MOSFETs
Diamond is a promising material for p-channel power field-effect transistors (FETs) due to its remarkable physical properties. However, no diamond FETs with current characteristics exceeding 1 A have so far been reported. P-channel FETs capable of high-current operation are essential in order to realize complementary inverters with n-channel wide bandgap devices such as SiC or GaN. In this work, we designed and fabricated vertical-type diamond metal-oxide-semiconductor FETs (MOSFETs) with a trench structure, and a gate width (${W} _{\text {G}}\text {)}$ of 0.1 to 10 mm. For devices with${W} _{\text {G}} =10$ mm and a source-drain voltage (${V} _{\text {DS}}\text {)}$ of –20 V, the drain current reached 0.7 A. We obtained a maximum drain current of over 1.5 A with${V} _{\text {DS}} =$ –20 V by connecting two devices in parallel within a chip. The drain current density and specific on-resistance at a${V} _{\text {DS}}$ of –10 V were 85 mA/mm and$118~\Omega \cdot $ mm, respectively (${W} _{\text {G}} =2$ mm). The leakage current in the off state is at the lower limit of the measurement ($\sim 10^{-{11}}$ A) and the on/off ratio is over nine orders of magnitude. - Open Access
- 1 January 2024
- Published by American Vacuum Society in Journal of Vacuum Science & Technology B
- Vol. 42 (1)
Influence of Al2O3 atomic-layer deposition temperature on positive-bias instability of metal/Al2O3/β-Ga2O3 capacitors
The influence of Al2O3 atomic-layer deposition (ALD) temperature on the electric characteristics of Al/Al2O3/(2¯01) β-Ga2O3 capacitors was investigated focusing on the positive-bias instability (PBI) of the capacitors. The current in the capacitors increased with ALD temperature, mostly because of the reduced energy barrier height for the electron field emission from the substrate and less negative Al2O3 charge, as revealed by the analysis conducted assuming a space-charge-controlled field emission process. The PBI tests were conducted for cumulative voltage stressing times vastly ranging from 3 × 10−6 to 4 × 105 s. The capacitance–voltage (C–V) characteristics of the capacitors for an ALD temperature of 100 °C displayed negative shifts in the middle of voltage stressing, unlike those for the other ALD temperatures. The bias stability of the capacitors was found to be considerably improved by high-temperature (450 °C) ALD. Additionally, the C–V characteristic shifts caused by the voltage stressing were theoretically reproduced quite accurately, assuming a model proposed in this study. In the simulations, the trap distributions in the Al2O3 films were assumed to be uniform both spatially and energetically. Importantly, the experimental results for various stressing voltages were excellently fitted by the simulations that assumed the same trap distribution. The trap densities in the Al2O3 films thus estimated reduced from 1.2 × 1020 to 2.2 × 1019 cm−3 eV−1 for ALD temperatures of 100–450 °C. This reduction in the trap densities was a major cause of the bias stability enhancement for high-temperature ALD. Moreover, the trap density as a function of ALD temperature qualitatively agreed with the aforementioned Al2O3 charge generated by the current measurements. This agreement provides a strong basis for the validity of the PBI model proposed in this study.
- 1 January 2024
- Published by American Vacuum Society in Journal of Vacuum Science & Technology B
- Vol. 42 (1)
Open AccessInfluence of Al2O3 atomic-layer deposition temperature on positive-bias instability of metal/Al2O3/β-Ga2O3 capacitors
The influence of Al2O3 atomic-layer deposition (ALD) temperature on the electric characteristics of Al/Al2O3/(2¯01) β-Ga2O3 capacitors was investigated focusing on the positive-bias instability (PBI) of the capacitors. The current in the capacitors increased with ALD temperature, mostly because of the reduced energy barrier height for the electron field emission from the substrate and less negative Al2O3 charge, as revealed by the analysis conducted assuming a space-charge-controlled field emission process. The PBI tests were conducted for cumulative voltage stressing times vastly ranging from 3 × 10−6 to 4 × 105 s. The capacitance–voltage (C–V) characteristics of the capacitors for an ALD temperature of 100 °C displayed negative shifts in the middle of voltage stressing, unlike those for the other ALD temperatures. The bias stability of the capacitors was found to be considerably improved by high-temperature (450 °C) ALD. Additionally, the C–V characteristic shifts caused by the voltage stressing were theoretically reproduced quite accurately, assuming a model proposed in this study. In the simulations, the trap distributions in the Al2O3 films were assumed to be uniform both spatially and energetically. Importantly, the experimental results for various stressing voltages were excellently fitted by the simulations that assumed the same trap distribution. The trap densities in the Al2O3 films thus estimated reduced from 1.2 × 1020 to 2.2 × 1019 cm−3 eV−1 for ALD temperatures of 100–450 °C. This reduction in the trap densities was a major cause of the bias stability enhancement for high-temperature ALD. Moreover, the trap density as a function of ALD temperature qualitatively agreed with the aforementioned Al2O3 charge generated by the current measurements. This agreement provides a strong basis for the validity of the PBI model proposed in this study.
- 1 January 2024
- Published by American Vacuum Society in Journal of Vacuum Science & Technology B
- Vol. 42 (1)
Influence of gate material and diamond surface termination on current conduction in metal/Al2O3/diamond capacitors
The current conduction in negatively biased metal/Al2O3/diamond capacitors with various gate materials and diamond surface terminations was comprehensively characterized by assuming a space-charge-controlled field emission (SCC-FE) process, yielding the following results. The current-feeding carriers were field-emitted from the electrode that had a barrier height lower than that of the opposing electrode. Specifically, in an Au-gate oxygen-terminated diamond capacitor, holes were likely to be emitted from the Al2O3/diamond interface states, whereas, in Al-gate oxygen-terminated, Au-gate hydrogen-terminated, and Al-gate hydrogen-terminated diamond capacitors, electrons were emitted from the gate. The barrier heights at the Al/Al2O3 and Au/Al2O3 interfaces were estimated as 1.6–1.7 and 2.8 eV, respectively. However, the analysis of the hole emission from the interface states is left for future studies. Although the substrate of the oxygen-terminated diamond capacitor remained weakly depleted even for highly negative gate voltages, the conduction current was observed as mentioned earlier. To analyze the mechanism for this conduction, the diffusion and drift currents in the depleted substrate were quantitatively estimated, ascribing the current conduction to the diffusion current. As these results could not be obtained by using the conventional graphical methods based on model-specific plots, such as the Fowler–Nordheim and Poole–Frenkel plots, the SCC-FE analysis proved to be a powerful tool for investigating the current conduction in metal-insulator-semiconductor capacitors.
- 1 January 2024
- Published by American Vacuum Society in Journal of Vacuum Science & Technology B
- Vol. 42 (1)
Influence of gate material and diamond surface termination on current conduction in metal/Al2O3/diamond capacitors
The current conduction in negatively biased metal/Al2O3/diamond capacitors with various gate materials and diamond surface terminations was comprehensively characterized by assuming a space-charge-controlled field emission (SCC-FE) process, yielding the following results. The current-feeding carriers were field-emitted from the electrode that had a barrier height lower than that of the opposing electrode. Specifically, in an Au-gate oxygen-terminated diamond capacitor, holes were likely to be emitted from the Al2O3/diamond interface states, whereas, in Al-gate oxygen-terminated, Au-gate hydrogen-terminated, and Al-gate hydrogen-terminated diamond capacitors, electrons were emitted from the gate. The barrier heights at the Al/Al2O3 and Au/Al2O3 interfaces were estimated as 1.6–1.7 and 2.8 eV, respectively. However, the analysis of the hole emission from the interface states is left for future studies. Although the substrate of the oxygen-terminated diamond capacitor remained weakly depleted even for highly negative gate voltages, the conduction current was observed as mentioned earlier. To analyze the mechanism for this conduction, the diffusion and drift currents in the depleted substrate were quantitatively estimated, ascribing the current conduction to the diffusion current. As these results could not be obtained by using the conventional graphical methods based on model-specific plots, such as the Fowler–Nordheim and Poole–Frenkel plots, the SCC-FE analysis proved to be a powerful tool for investigating the current conduction in metal-insulator-semiconductor capacitors.
- 8 September 2023
- Published by Japan Society of Applied Physics
Radiation Effects on 2DHG Diamond MOSFETs with Boron-doped Source and Drain Layers
2023 International Conference on Solid State Devices and Materials ,Radiation Effects on 2DHG Diamond MOSFETs with Boron-doped Source and Drain Layers
- 8 September 2023
- Published by Japan Society of Applied Physics
Radiation Effects on 2DHG Diamond MOSFETs with Boron-doped Source and Drain Layers
2023 International Conference on Solid State Devices and Materials ,Radiation Effects on 2DHG Diamond MOSFETs with Boron-doped Source and Drain Layers
- 26 September 2022
- Published by AIP Publishing in Journal of Applied Physics
- Vol. 132 (12) , 125702
Capacitance–voltage characterization of metal–insulator–semiconductor capacitors formed on wide-bandgap semiconductors with deep dopants such as diamond
As diamond possesses only deep dopants, certain conventional physics and characterization methods are not applicable to diamond devices, owing to the explicit or implicit assumption of shallow dopants. To resolve this limitation, the capacitance–voltage (C–V) characteristics of metal–insulator–semiconductor (MIS) capacitors formed on a semiconductor substrate with deep and compensating dopants were successfully formulated. Based on these equations, methods for accurately estimating the MIS capacitor properties were developed and validated through their application in the analysis of an actual MIS capacitor formed on a boron-doped hydrogen-terminated diamond substrate. The high-frequency C–V characteristic of the capacitor exhibited a prominent dip specific to deep dopants. However, the dip depth was considerably shallower than theoretically expected. This C–V characteristic was accurately reproduced theoretically, assuming the presence of a surficial diamond layer that contains acceptors with an activation energy of 0.23 eV, which is less than the value 0.37 eV for boron, and has a thickness of the extrinsic Debye length (40 nm in this study) or larger. The insulator charge of the MIS capacitor was estimated as −4.6 × 1012 cm−2 in units of electronic charge, which is sufficiently large to induce two-dimensional hole gas. The interface-state density was 1.4 × 1012 cm−2 eV−1 for interface-state energies of 0.3–0.5 eV above the valence band maximum. Hence, the proposed methodology and the possible presence of the reduced activation energy layer will guide the development of diamond-based devices.
- 26 September 2022
- Published by AIP Publishing in Journal of Applied Physics
- Vol. 132 (12) , 125702
Capacitance–voltage characterization of metal–insulator–semiconductor capacitors formed on wide-bandgap semiconductors with deep dopants such as diamond
As diamond possesses only deep dopants, certain conventional physics and characterization methods are not applicable to diamond devices, owing to the explicit or implicit assumption of shallow dopants. To resolve this limitation, the capacitance–voltage (C–V) characteristics of metal–insulator–semiconductor (MIS) capacitors formed on a semiconductor substrate with deep and compensating dopants were successfully formulated. Based on these equations, methods for accurately estimating the MIS capacitor properties were developed and validated through their application in the analysis of an actual MIS capacitor formed on a boron-doped hydrogen-terminated diamond substrate. The high-frequency C–V characteristic of the capacitor exhibited a prominent dip specific to deep dopants. However, the dip depth was considerably shallower than theoretically expected. This C–V characteristic was accurately reproduced theoretically, assuming the presence of a surficial diamond layer that contains acceptors with an activation energy of 0.23 eV, which is less than the value 0.37 eV for boron, and has a thickness of the extrinsic Debye length (40 nm in this study) or larger. The insulator charge of the MIS capacitor was estimated as −4.6 × 1012 cm−2 in units of electronic charge, which is sufficiently large to induce two-dimensional hole gas. The interface-state density was 1.4 × 1012 cm−2 eV−1 for interface-state energies of 0.3–0.5 eV above the valence band maximum. Hence, the proposed methodology and the possible presence of the reduced activation energy layer will guide the development of diamond-based devices.
- 23 March 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 69 (5) , 2236-2242
−10 V Threshold Voltage High-Performance Normally-OFF C–Si Diamond MOSFET Formed by p+-Diamond-First and Silicon Molecular Beam Deposition Approaches
In this article, the normally- OFF oxidized Si-terminated (C–Si) diamond metal–oxide–semiconductor field-effect transistors (MOSFETs) with as-deposited 0.5-nm silicon on diamond annealed at high temperature as the subsurface p-channel were presented for the first time. A novel method utilizing both a metal mask to realize the regrown heavily boron-doped (001) diamond layer first (p + -diamond-first) and a molecular beam deposition (MBD) method to procure atomic-scale silicon deposition was achieved. Scanning transmission electron microscopy (STEM) and energy-dispersive X-ray spectroscopy (EDS) element mapping results suggest that the C–Si diamond/Al 2 O 3 interface is quite continuous and atomically flat. A remarkably high threshold voltage (${V}_{\text{TH}}$ ) of −10 V and a maximum drain current density (${I}_{D\_{}{\text{MAX}}}$ ) of −156 mA/mm are simultaneously achieved in the fabricated devices. The devices with different source and drain (S/D) distances ($L_{\text{SD}}$ ) deliver robust${V}_{\text{TH}}$ results and feature low OFF-state S/D leakage current$\vert {I}_{\text{leakage}}\vert $ of ~$6\times10$ −6 mA/mm at${V}_{\text{GS}}$ = 0 V. The extracted field-effect mobility is as high as 127 cm 2$\cdot \text{V}$ −1$\cdot \text{s}$ −1 and the interface state density is as low as$4.35\times10$ 12 eV −1$\cdot $ cm −2 . These competitive results reveal that this first attempt of employing the combination of p + -diamond-first and MBD approaches promotes the integration of the advanced silicon manufacturing process with wide bandgap diamond material for power applications.- 23 March 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 69 (5) , 2236-2242
−10 V Threshold Voltage High-Performance Normally-OFF C–Si Diamond MOSFET Formed by p+-Diamond-First and Silicon Molecular Beam Deposition Approaches
In this article, the normally- OFF oxidized Si-terminated (C–Si) diamond metal–oxide–semiconductor field-effect transistors (MOSFETs) with as-deposited 0.5-nm silicon on diamond annealed at high temperature as the subsurface p-channel were presented for the first time. A novel method utilizing both a metal mask to realize the regrown heavily boron-doped (001) diamond layer first (p + -diamond-first) and a molecular beam deposition (MBD) method to procure atomic-scale silicon deposition was achieved. Scanning transmission electron microscopy (STEM) and energy-dispersive X-ray spectroscopy (EDS) element mapping results suggest that the C–Si diamond/Al 2 O 3 interface is quite continuous and atomically flat. A remarkably high threshold voltage (${V}_{\text{TH}}$ ) of −10 V and a maximum drain current density (${I}_{D\_{}{\text{MAX}}}$ ) of −156 mA/mm are simultaneously achieved in the fabricated devices. The devices with different source and drain (S/D) distances ($L_{\text{SD}}$ ) deliver robust${V}_{\text{TH}}$ results and feature low OFF-state S/D leakage current$\vert {I}_{\text{leakage}}\vert $ of ~$6\times10$ −6 mA/mm at${V}_{\text{GS}}$ = 0 V. The extracted field-effect mobility is as high as 127 cm 2$\cdot \text{V}$ −1$\cdot \text{s}$ −1 and the interface state density is as low as$4.35\times10$ 12 eV −1$\cdot $ cm −2 . These competitive results reveal that this first attempt of employing the combination of p + -diamond-first and MBD approaches promotes the integration of the advanced silicon manufacturing process with wide bandgap diamond material for power applications.