Mattias Borg

We use a closed-loop algorithm to accurately program hafnium zirconium oxide (HZO) ferroelectric tunnel junctions (FTJs) to arbitrary chosen target conductance values. The key enabler is suppression of conductance growth. We have identified two different mechanisms contributing to the total conductance of FTJs. By controlling both, we demonstrated an up to threefold increase of the usable conductance range, allowing for 192 distinct states to be reliably programmed. Retention of the programmed states is independent of the absolute conductance level, allowing for 6-bit precision to be achievable for 22 min in the extended range. An additional benefit of suppressing conductance growth is a 100-fold extension of the device endurance.

Artificial intelligence (AI) is set to disrupt the way businesses and civil society operate, but the large energy usage for training and running AI compute models remains a pressing concern in terms of its sustainability. Analog in-memory computing (AIMC) hardware based on memristor devices is a promising route to significant energy-savings. Among the various memristor technologies, ferroelectric tunnel junctions (FTJs) hold considerable promise for large scale AIMC. Their performance prospects remain to be fully assessed; therefore, we here evaluate the viability of FTJ memristors as compute units for AIMC. Based on the behavior of experimental TiN/HfZrO₄/W FTJs we define three operating modes which we apply to standard AI tests and two real-world use cases: Image segmentation (YOLOv8) and natural language processing (BERT). We find that the inherent mechanism behind the analog state in FTJs limits the usable dynamic range and thus enforces strict control of noise. The best overall performance is obtained by constricting the dynamic range further and using ultrashort programming pulses (0.5 ns); on BERT matching the performance of digital hardware. We also present a more accessible approach, combining three FTJs, two of which are operated as binary memories, to achieve similar performance while also relaxing the requirements on data converter precision and level of noise. All in all, we here reveal benefits and intrinsic challenges of FTJ-based AIMC systems, providing a blueprint for future experimental implementations.

Artificial intelligence (AI) is set to disrupt the way businesses and civil society operate, but the large energy usage for training and running AI compute models remains a pressing concern in terms of its sustainability. Analog in-memory computing (AIMC) hardware based on memristor devices is a promising route to significant energy-savings. Among the various memristor technologies, Ferroelectric Tunnel Junctions (FTJs) hold considerable promise for large scale AIMC. Their performance prospects remain to be fully assessed; therefore, we here evaluate the viability of FTJ memristors as compute units for AIMC. Based on the behavior of experimental TiN/HfZrO4/W FTJs we define three operating modes which we apply to standard AI tests and two real-world use cases: Image segmentation (YOLOv8) and natural language processing (BERT). We find that the inherent mechanism behind the analog state in FTJs limits the usable dynamic range and thus enforces strict control of noise. The best overall performance is obtained by constricting the dynamic range further and using ultrashort programming pulses (0.5 ns); on BERT matching the performance of digital hardware. We also present a more accessible approach, combining three FTJs, two of which are operated as binary memories, to achieve similar performance while also relaxing the requirements on data converter precision and level of noise. All in all, we here outline benefits and intrinsic challenges of FTJ-based AIMC systems, providing a blueprint for future experimental implementations.

Nonvolatile memory devices based on ferroelectric Hf_xZr_1-xO₂ (HZO) show great promise for back-end integrable storage and for neuromorphic accelerators, but their adoption is held back by the inability to scale down the HZO thickness without violating the strict thermal restrictions of the Si CMOS back end of line. In this work, we overcome this challenge and demonstrate the use of nanosecond pulsed laser annealing (NLA) to locally crystallize areas of an ultrathin (3.6 nm) HZO film into the ferroelectric orthorhombic phase. Meanwhile, the heat induced by the pulsed laser is confined to the layers above the Si, allowing for back-end compatible integration. We use a combination of electrical characterization, nanofocused scanning X-ray diffraction (nano-XRD), and synchrotron X-ray photoelectron spectroscopy (SXPS) to gain a comprehensive view of the change in material and interface properties by systematically varying both laser energy and the number of laser pulses on the same sample. We find that NLA can provide remanent polarization up to 2P_r= 11.6 μC/cm² in 3.6 nm HZO, albeit with a significant wake-up effect. The improved TiN/HZO interface observed by XPS explains why device endurance goes beyond 10⁷ cycles, whereas an identical film processed by rapid thermal processing (RTP) breaks already after 10⁶ cycles. All in all, NLA provides a promising approach to scale down the ferroelectric oxide thickness for emerging HZO ferroelectric devices, which is key for their integration in scaled process nodes.

Neuromorphic computing has seen great interest as leaps in artificial intelligence (AI) applications have exposed limitations due to heavy memory access, with the von Neumann computing architecture. The parallel in‐memory computing provided by neuromorphic computing has the potential to significantly improve latency and power consumption. Key to analog neuromorphic computing hardware are memristors, providing non‐volatile multistate conductance levels, high switching speed, and energy efficiency. Ferroelectric tunnel junction (FTJ) memristors are prime candidates for this purpose, but the impact of the particular characteristics for their performance upon integration into large crossbar arrays, the core compute element for both inference and training in deep neural networks, requires close investigation. In this work, a W/Hf _x Zr_1−x O₂/TiN FTJ with 60 programmable conductance states, a dynamic range (DR) up to 10, current density >3 A m⁻² at V _read = 0.3 V and highly nonlinear current–voltage (I–V) characteristics (>1100) is experimentally demonstrated. Using a circuit macro‐model, the system level performance of a true crossbar array is evaluated and a 92% classification accuracy of the modified nation institute of science and technology (MNIST) dataset is achieved. Finally, the low on conductance in combination with the highly nonlinear I–V characteristics enable the realization of large selector‐free crossbar arrays for neuromorphic hardware accelerators.

Ferroelectric hafnium and zirconium oxides have undergone rapid scientific development over the last decade, pushing them to the forefront of ultralow-power electronic systems. Maximizing the potential application in memory devices or supercapacitors of these materials requires a combined effort by the scientific community to address technical limitations, which still hinder their application. Besides their favorable intrinsic material properties, HfO2–ZrO2 materials face challenges regarding their endurance, retention, wake-up effect, and high switching voltages. In this Roadmap, we intend to combine the expertise of chemistry, physics, material, and device engineers from leading experts in the ferroelectrics research community to set the direction of travel for these binary ferroelectric oxides. Here, we present a comprehensive overview of the current state of the art and offer readers an informed perspective of where this field is heading, what challenges need to be addressed, and possible applications and prospects for further development.

3D integration of III-V semiconductors with Si CMOS is highly attractive since it allows combining new functions such as photonic and analog devices with digital signal processing circuitry. Thus far, most 3D integration approaches have used epitaxial growth on Si, layer transfer by wafer bonding, or die-to-die packaging. Here we present low-temperature integration of InAs on W using Si₃N₄ template assisted selective area metal-organic vapor-phase epitaxy (MOVPE). Despite growth nucleation on polycrystalline W, we can obtain a high yield of single-crystalline InAs nanowires, as observed by transmission electron microscopy (TEM) and electron backscatter diffraction (EBSD). The nanowires exhibit a mobility of 690 cm²/(V s), a low-resistive, Ohmic electrical contact to the W film, and a resistivity which increases with diameter attributed to increased grain boundary scattering. These results demonstrate the feasibility for single-crystalline III-V back-end-of-line integration with a low thermal budget compatible with Si CMOS.

In this work, we evaluate the importance of the postmetallization annealing (PMA) temperature on the performance of HfxZr1−xO2-based ferroelectric tunnel junctions (FTJs). Our results indicate a significant difference in tunneling electroresistance (TER) ratio and endurance, depending on the PMA temperature despite negligible variations in remanent polarization. We conclude that the minimization of conductive oxide defect states is central to achieve high performance. Through carefully optimized PMA conditions, we demonstrate FTJs with a TER = 3 and low mean cycle-to-cycle variation of < 1.5% combined with at least 16 separable conductance states providing a 4-bit resolution analog FTJ.

In this study, we report the optical and material characteristics of an InSb nanostructure photodetector integrated directly on Si using rapid melt growth.

Ferroelectric Hf_xZr_1–xO₂ (HZO) is typically achieved by crystallization of an amorphous thin film via rapid thermal processing (RTP) at time scales of seconds to minutes. For integration on III–V semiconductors, this approach can severely degrade the sensitive HZO/III–V interface. To evaluate whether a reduced thermal budget can improve the interface quality, millisecond duration thermal anneals are utilized using a flash lamp annealer (FLA) on HZO/InAs capacitors. Through thorough electrical characterization such as polarization hysteresis, endurance, and capacitance‐voltage measurements, as well as synchrotron‐based chemical interface characterization, the FLA and RTP treatments are compared and the FLA results are found in lower interface defect density and higher endurance, but also have generally lower remanent polarization (P_r) compared to RTP. Additionally, ways to achieve high P_r and low interface defect density using multiple lower energy flashes, as well as by pre‐crystallization during the ALD growth step are investigated. Using FLA, P_r exceeding 20 µC cm⁻² is achieved, with extended endurance properties compared to RTP treatment and a considerably decreased defect density, indicative of a higher quality HZO/InAs interface. This work presents valuable insight into the successful integration of ferroelectric HZO on low thermal budget III–V semiconductors.