Jeebananda Panda

This paper presents proposed multi mode memory PUF design for high speed 5G IOT nodes. Since in conventional IOT nodes keys are used to be stored in non volatile memory, This will cause the side channel vulnerability and compromise the integrity. Silicon PUFs are used as feasible solution for this. However there is vulnerabilities in existed PUF architectures. To overcome these a new multi mode memory PUF was designed. This new PUF can be operated in two modes i.e Weak PUF(W) mode Strong(S) PUF mode. Authentication by Strong mode and weak Mode are discussed. The performance evolution metrics of proposed PUFs are close to ideal responses. The vulnerability analysis and possible side channel attacks such as data remanance attack and modeling attacks already performed in the existed memory PUFS were discussed and counter measures are used to design novel PUF of this work. The work is implemented on Artix-7 FPGA The authentication by S mode PUF and W mode PUF for IOT is implemented. The key generation by using W mode is implemented. The propose PUF has uniqueness is 49.96 %, uniformity is 49.87%, BER is 0.41

In this article, a new true random number generator (TRNG) with out ring oscillators is presented to suit advanced cloud-based Field Programmable Gate Array (FPGA). For example Amazon Web Service (AWS) EC2 F1 restrict ring oscillators to generate True random numbers. This design is compatible to all cloud based FPGA providers because in our design not having any Ring oscillator stage to produce random outputs. Our design is based on hybrid arbiter controller with closed feedback mechanism. This novel design is immune to photon emission and fault injection side channel attacks. Our TRNG implemented on Artix-7 FPGA with only 168 LUT, 40Flip flops, 69 slices and through put 8.6.

Silicon based PUF uses manufacturing process variations to generate PUF signature to protect from side channel attacks. In this paper a new hybrid PUF design has been implemented on FPGA with programmable delays with Galois RO and glitch architectures. The proposed PUF is immune to existing side channel vulnerabilities such as EM emissions, modelling attacks etc. To generate unit bit response the designed PUF occupies lower area than literature. The novel architecture has improved uniqueness, uniformity, reliability. The randomness is increased by programmable delays, Galois architectures and glitch circuits. The proposed PUF has uniformity of 49.78%, Bit Error Rate (BER) is 0.35%, uniqueness 49.38% and reliability of PUF is around 99.7%.