David Jiménez

Correlated mobility fluctuations are considered in the physics-based carrier number fluctuation ( $\boldsymbol {\Delta }\textit {N}$ ) low-frequency noise (LFN) compact model of single-layer (SL) graphene field-effect transistors (GFET) in the present study. Trapped charge density and Coulomb scattering coefficient $\boldsymbol {\Delta }{N}$ LFN parameters are obtained after applying a parameter extraction methodology, adapted from conventional silicon technologies, to the linear ambipolar regions of GFETs. Appropriate adjustments are considered in the method according to GFETs’ physical characteristics. Afterward, Hooge mobility as well as series resistance fluctuations, LFN parameters can be extracted. The updated LFN model is validated with experimental data from various long and short-channel GFETs at an extended range of gate and drain bias conditions.

This work proposes a methodology entirely based on processing S-parameters to determine the gate-to-source voltage-dependent mobility of charge carriers in the graphene field-effect transistor channel, without requiring any information about the material properties. Furthermore, regressions from experimental data of transistor arrays with different geometries are not required, thus avoiding uncertainties related to process variations and device-to-device measurement conditions. Hence, one key advantage of this method is its applicability to analyze the performance of different devices under the same operating conditions, or the performance of a single device under varying conditions. As part of the methodology, the effects of the parasitic series resistances associated with the source and drain access paths are considered, thereby overcoming the well-known disadvantage of direct-current methods, where the corresponding de-embedding is cumbersome. This method has been used to determine the carrier mobility in graphene within a gate-to-source voltage range, starting from the Dirac voltage and extending to the region where electron conduction dominates. A small-signal model with the extracted parameter values shows an excellent agreement with the experimental S-parameters up to 20 GHz for the dynamic response of different devices, including two devices that have not been used during parameter extraction. Throughout the development and application of the proposal, a mobility model accounting for the degradation caused by the transverse electric field has been considered.

For the growth of emerging graphene field-effect transistor (GFET) technologies, a thorough characterization of on-wafer variability is required. Here, we report for the first time a physics-based compact model, which precisely describes the drain current (I_D) fluctuations of monolayer GFETs. Physical mechanisms known to generate 1/f noise in transistors, such as carrier number and Coulomb scattering mobility fluctuations, are also revealed to cause I_D variance. Such effects are considered in the model by being activated locally in the channel and the integration of their contributions from source to drain results in total variance. The proposed model is experimentally validated from a statistical population of three different-sized solution-gated (SG) GFETs from strong p-to strong n-type bias conditions. A series resistance I_D variance model is also derived mainly contributing at high carrier densities.

The mobility-degradation-based model for the drain-to-source or output resistance of a graphene field-effect transistor (GFET) is linearized here using a Taylor series approximation. This simplification is shown to be valid from the magnitudes of the gate voltage not significantly higher than the Dirac voltage, and it enables the analytical determination of the transconductance parameter, the voltage related to residual charges, and a bias-independent series resistance of the GFET. Furthermore, a continuous representation of the device’s static response is achieved when substituting the extracted parameters into the model, regardless the transfer characteristic symmetry with respect to the Dirac voltage.

The main target of this article is to propose for the first time a physics-based continuous and symmetric compact model that accurately captures I–V experimental dependencies induced by geometrical scaling effects for graphene field-effect transistor (GFET) technologies. Such a scalable model is an indispensable ingredient for the boost of large-scale GFET applications, as it has been already proved in solid industry-based CMOS technologies. Dependencies of the physical model parameters on channel dimensions are thoroughly investigated, and semi-empirical expressions are derived, which precisely characterize such behaviors for an industry-based GFET technology, as well as for others developed in research laboratory. This work aims at the establishment of the first industry standard GFET compact model that can be integrated in circuit simulation tools and, hence, can contribute to the update of GFET technology from the research level to massive industry production.

Graphene field-effect transistors (GFETs) exhibit negligible transconductance under two scenarios: for any gate-to-source voltage when the drain-to-source voltage is set to zero and for an arbitrary drain-to-source voltage provided that the gate-to-source voltage equals the Dirac voltage. Hence, extracting the channel and the parasitic series resistances from S -parameters under these conditions enables analyzing their dependence on the gate and drain biases. This is fundamental to assess the portion of the output resistance that is controlled by the gate. Besides, the drain bias dependence of the drain and source resistances is also evidenced. Within the proposal, resistive components accounting for the lossy nature of the gate capacitance are incorporated into the model, which exhibits a broadband correlation with experimental data. This avoids the series resistances to be considered as frequency dependent in the model.

Exploiting ambipolar electrical conductivity based on graphene field‐effect transistors has raised enormous interest for high‐frequency (HF) analog electronics. Controlling the device polarity, by biasing the graphene transistor around the vertex of the V‐shaped transfer curve, enables to redesign and highly simplify conventional analog circuits, and simultaneously to seek for multifunctionalities, especially in the HF domain. This study presents new insights for the design of different HF applications such as power amplifiers, mixers, frequency multipliers, phase shifters, and modulators that specifically leverage the inherent ambipolarity of graphene‐based transistors.

We present a physics-based compact model of graphene field-effect transistors (GFETs) able to be run under the freeware Quite Universal Circuit Simulator (QUCS), bringing the possibility to any user to undertake circuit simulations based on the emergent graphene technology. The model is based on the drift-diffusion mechanism for the carrier transport coupled with the solution of the electrostatics of the device structure. Simulations on QUCS of an exemplary application consisting of a GFET-based gas sensor are shown, bringing to light the potential of the technology computer-aided design (TCAD) tool developed for novel concepts of applications based on the inherent features of graphene and related materials.