Yung-Hui Chung

This paper presents a 16-bit successive approximation register analog-to-digital converter (ADC) achieving over-100 dB spurious-free dynamic range (SFDR). This ADC uses V_CM-based and binary-window digital-to-analog converter (DAC) switching schemes to improve the signal-to-noise and distortion ratio (SNDR). Moreover, a level-2 capacitor swapping scheme is proposed to achieve superior DAC linearity by using two intrinsic true random number sequences. A prototype ADC is fabricated in 180 nm CMOS technology and occupies an active area of 0.53 mm². At 1 MS/s, it consumes a total power of 1.05 mW from a supply of 1.8 V. The measured differential and integral nonlinearity are −0.65/+0.45 and −2.2/+2.1 least significant bit. With an input of 1 kHz, the measured SNDR and SFDR are 83 dB and 100 dB. The effective number of bits is 13.5, which is equivalent to a Schreier figure-of-merit of 169.8 dB.

This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) that uses a digital-to-analog converter (DAC) configurable window switching technique. By reusing the capacitors in the DAC, the proposed window switching scheme yields window boundaries to determine whether the input is located within the window, and thus avoid unnecessary capacitor switching. The proposed window SAR ADC improves the conversion efficiency and ADC linearity. A qualitative analysis of prior window switching schemes is presented to elaborate for various applications. A low-input capacitance of 1 pF was adopted to relax the input and reference buffers. A prototype ADC was implemented in 180-nm CMOS occupying an active area of 0.1 mm². At 20 MS/s, it consumes a total power of 1.22 mW from a 1.5-V supply. The measured peak signal-to-noise and distortion ratio and spurious-free dynamic range were 61.7 and 79 dB, respectively. At the Nyquist rate, the measured effective number of bits (ENOB) was 9.53, equivalent to a figure-of-merit (FOM) of 83 fJ/conversion-step. In low-power mode (100 kS/s), it consumed a total power of 1.5μW from a 0.7-V supply. At the Nyquist rate, the measured ENOB was 9.82, equivalent to a FOM of 16.6 fJ/conversion step.

This paper presents a 12-bit 2-way time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). This study applied the master clock sampling and gain/offset correction schemes to mitigate channel mismatch errors. In the channel ADC, the subrange SAR ADC architecture was used to maintain high-speed and low-power features. A common bootstrapping circuit was proposed for suppressing the sampling error between coarse and fine ADCs. An intrinsic random sequence was applied to the capacitor swapping. The prototype ADC was fabricated using 65-nm CMOS technology, and it consumed 3 mW from a 1.2-V supply at a sampling rate of 160-MS/s. The measured peak signal-to-noise ratio and spurious-free dynamic range were 60.5 and 80 dB, respectively. The measured peak effective number of bits was 9.76, which is equivalent to a figure-of-merit of 21.6 fJ/conversion-step.

This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The subrange SAR ADC architecture is applied to achieve 100-MS/s. A foreground offset tracking scheme is proposed to reduce the offset deviation between the coarse and fine ADCs. A simple binary-window DAC switching scheme is applied to maintain both the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR). The prototype SAR ADC was implemented using a 65-nm CMOS technology. At 100-MS/s, it consumed a total power of 1.9 mW from a 1.2 V supply. The measured differential nonlinearity and integral nonlinearity were -0.8/+1.6 LSB and -1.2/+1.2 LSB, respectively. The peak SNDR and SFDR were 61.5 dB and 81 dB, respectively. At the Nyquist rate, the measured effective number of bits was 9.8, which is equivalent to a figure-of-merit of 21.3 fJ/conversion-step.

This paper presents a 12-bit 40-MS/s successive approximation register analog-to-digital converter (ADC) for ultrasound imaging systems. By incorporating a fast binary window digital-to-analog converter (DAC) switching technique, the problematic most significant bit transition glitch was removed to improve linearity without increasing the input capacitance or using a calibration scheme. A hybrid DAC was also developed to overcome the yield problem that occurs when a tiny unit capacitance is used in the DAC. Moreover, a reference buffer was used to accelerate the DAC settling to achieve high-speed conversion. The prototype ADC was fabricated using a 130-nm CMOS technology. The ADC core occupied an active area of 0.1 mm² and consumed a total power of 1.32 mW when a 1.2-V supply was used at a conversion rate of 40 MS/s. The measured peak signal-to-noise-and-distortion ratio and spurious-free dynamic range were 64 and 77.5 dB, respectively. The peak effective number of bits was 10.33, which is equivalent to a Walden figure-of-merit of 25.6 fJ/conversion step.

This study presents a 6-bit domino successive approximation register (SAR) analog-to-digital converter (ADC). The proposed domino-SAR ADC architecture provides high-speed domino operation and the offset immunity of SAR ADCs. The ping-pong operation enacts a master clock sampling scheme to achieve a sampling rate of 1.3 GHz. A prototype ADC chip was fabricated using a 55-nm CMOS technology. The chip consumes a total power of 3.5 mW from a 1.2-V power supply. The measured peak SNDR and SFDR are 33 dB and 48 dB, respectively. The peak effective number of bits is 5.2 bits, equivalent to the figure of merit of 73 fJ/conversion step.

This paper presents an 11-bit successive approximation register (SAR) analog-to-digital converter (ADC). The subranged-SAR ADC architecture is applied to achieve a sampling rate of 100 MHz. The proposed gain error compensation helps attenuate the gain error between coarse and fine ADCs. An up-then-down digital-to-analog converter (DAC) switching scheme is used to maintain a small common-mode variation for the fine comparator. To maintain a good spurious free dynamic range (SFDR), the capacitor-swapping scheme is applied in the DAC. The prototype ADC was implemented using a 65-nm CMOS technology. It consumes a total power of 2.4 mW from a 1.2-V supply. The measured peak signal-to-noise-and-distortion ratio and SFDR are 61.1 and 85 dB, respectively. The peak effective number of bits is 9.86, equivalent to a figure-of-merit of 25.8 fJ/conversion step.

Summary: This paper presents an energy‐efficient 12‐bit successive approximation‐register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary‐window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious‐free dynamic range and signal‐to‐noise‐and‐distortion ratio. The ADC prototype occupies an active area of 0.12 mm²in the 0.18‐μm CMOS process and consumes a total power of 0.6 mW from a 1.5‐V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7‐dB signal‐to‐noise‐and‐distortion ratio and 83‐dB spurious‐free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure‐of‐merit of 43 fJ/conversion‐step.