Joseph Shor

This article presents a novel sensing scheme for a 2T gain-cell embedded dynamic random access memory (GC-eDRAM) optimized for cryogenic temperatures. The proposed design integrates a highly accurate sense amplifier (SA) with a $\pm 3\sigma $ sensitivity of 11.16 mV and an internally generated, adjustable reference voltage (VREF) with 9.5 mV step resolution. Additionally, an on-chip ring-oscillator-based design-for-test (RO-DFT) mechanism is introduced to determine the optimal VREF postfabrication, improving readout reliability while adapting to process variations. Simulation results, based on a 65nm CMOS process calibrated for 77 K operation, demonstrate a significant extension of the data retention time (DRT) to 80 ms, reducing refresh cycle frequency and lowering power consumption—critical for cryogenic applications such as infrared imaging. The proposed architecture provides a power-efficient, high-density embedded memory solution for low-temperature computing environments.

A BJT based resistor-less bandgap reference circuit in 65nm CMOS is presented. High impedance switched-capacitor-based resistors replace the standard diffusion resistors in a current mode architecture. Switch conductance and leakage are controlled by an internally generated boosted voltage and a negative clock signal circuit. To start up the BGREF, a low current injection method is applied in sensitive nodes of the design. The circuit occupies 0.0106 mm ${}^{\mathbf {2}}$ and has a power consumption of 8 nW from a 0.85 V supply. Independent trimming of the temperature coefficient and output voltage is presented, both of which are required for high volume manufacturing. After a two-point calibration process, a measurement of 31 units exhibited a mean temperature drift of 111 ppm/°C, a PSRR of -38 dB and an accuracy of 0.59% at $30~^{\circ }$ C.

A new architecture of an on-die process monitor circuit is demonstrated in 28nm. The proposed circuit can extract the threshold voltage, VTH, and random mismatch of a transistor using multiple extraction methods including the second derivative method. A sigma-delta modulator analog-to-digital converter samples the output to enable on-die processing of the results. A VDS voltage control loop enables VTH extraction in both the linear and saturation regions of the device. The circuit has a compact area of 5510 μm2.

A fully integrated ultra-low-power step-down DC-DC converter in 65nm is presented. The purpose of this converter is to convert battery voltage levels, in the range of 2.5-3V, to digital and mixed-signal voltage levels for low-power always-on domains. A down-conversion with a ratio of 5:1 is employed to provide a digital voltage level near the threshold voltage (Vth), which ranges from 0.55-0.6V. Higher voltage levels, such as 1.2V and 1.8V, are also made available for analog circuits. To achieve high-speed regulation at low power, an inverter-based comparator is utilized. Silicon results indicate an Efficiency-Enhancement-Factor (EEF) of 66% and a power density of 2.56 mW/mm ² at an output power of 100μW. These parameters represent the state-of-the-art for this level of power. The DC-DC converter exhibits a fast transient response, leading to minimal droops and overshoots, even for a 50pF output capacitor.

A Dynamic Continuous-Time Zoom-ADC current to digital converter for bio-sensing applications is presented, comprising a current DAC (IDAC), a loop filter, a comparator, and loop logic. Within the IDAC, a reference voltage is driven to resistor legs, obtaining an accurate current with high Rout. A 1 $^{\mathrm{st}}$ order loop filter utilizes an inherently linear, zero-static-power, passive integrator. An isolation of the integrator from external sensor capacitance is obtained by a cascode transistor, enabling the use of the passive integrator. During the Zoom’s SAR phase, a binary search detects the approximate signal level and provides zoomed references for the Sigma-Delta phase, where fine conversion is performed. The dynamic mode tracks the comparator output data to determine when the input signal is close to the references and updates them accordingly. This paper is the first to propose a dynamic zoom ADC which utilizes a single DAC. An over-voltage detector detects integrator voltages exceeding the supply level, a result of high input currents, and prevents damage to the circuit. A 65nm implementation achieved a competitive dynamic range of 125dB, an SNR of 91dB and an FoM of 192dB. The design occupies 0.08 mm $^{2}$ , and a state-of-the-art power consumption of 11.4uW was measured. The dynamic mode supports up to 78Hz inputs, and an SFDR of 90.4dB was measured.

Photodiodes can be utilized for both image sensing and energy harvesting, but at opposite polarity. There have been numerous research works which have attempted a self-powered imager, by flipping the diodes and harvesting. However, the integration cycle in the image sensing process is very long and the chip cannot harvest while in this mode. In this paper, an event detector (ED) function is demonstrated in 180nm, whereby the voltage across the photodiode is monitored during harvesting. If there is a significant change in this voltage, then an event is detected, and the chip can take a picture. Two types of event detectors are proposed, which can function at average power as low as 0.2-1μW.

Voltage level detectors (VLD) are used to monitor the supply voltage in integrated circuits (ICs) to determine when the system can initiate computation. The VLD must detect its own supply voltage, which is more challenging for low-voltage applications such as near- $V_{\mathrm {TH}}$ computing (NVTC), which also requires low latency and rapid supply changes; furthermore, internal races in the VLD may cause false indications or glitches in the system and should be prevented by design. This work presents a glitch-free VLD that can detect supplies as low as 385 mV at a power of 217 nW and a measured latency of 10 $\mu \text{s}$ . This was achieved by inserting a deterministic delay into one of the internal nodes, as well as low-voltage circuitry. The circuit is fabricated in a 65 nm CMOS process and occupies a footprint of 6900 $\mu \text{m}^{2}$ with a measured temperature drift of 105 $\mu \text{W}/^{\circ }\text{C}$ and a sigma variation of 8 mV across 32 units. These characteristics make the circuit attractive for the near-threshold computing segment.

A nW-level BJT-based bandgap reference with fine grained voltage and temperature coefficient trimming is presented. The bandgap reference utilizes switched capacitors (SC) as impedance elements instead of resistors in a current mode configuration. This configuration enabled low power (38nW) with a minimal area (0.0174 mm2). The voltage could be trimmed independently without affecting the temperature coefficient. The SC’s are stacked in order to achieve accurate trimming without using unrealistically small capacitors. The temperature coefficient can be trimmed between 50-200 ppm/°C in either direction, while the voltage can be trimmed between 580-800mV.

The most prevalent industrial PUFs (physical unclonable functions) utilize SRAM-based designs. Bit stability is one of the fundamental problems in PUF design. PUF circuits, which rely on silicon manufacturing mismatches to produce a random key, are vulnerable to cases where the mismatch is insufficient and noise affects the PUF response, rendering it unstable. This brief provides a tutorial about SRAM-based PUFs stable bits preselection, utilizing an embedded tilt test. This method is more efficient than existing error correction codes in terms of power, area and latency. During the test, external, controlled mismatch, tilts the PUF cells against their manufactured mismatch and cells that retain their response are considered stable. In this tutorial, the preselection method is explained, implementation examples are presented, and a method to further exploit the test to obtain more uncorrelated stable bits from the existing PUF structure is introduced.

Temperature monitoring and regulation is a critical power/performance feature in microprocessors. Due to the multiplicity of hotspots, a large number of on-die sensors are utilized. This requires them to be highly compact, low energy and fast. A miniaturized current controlled oscillator (CCO) sensor is described for this application. It has an area of only 700 $\mu \text{m}^{2}$ in the 16-nm FinFET process, with an energy consumption of 0.25 nJ in a 6.9- $\mu \text{s}$ conversion. The inaccuracy is within ±1.5 °C peak-to-peak (p-p) over a 130 °C range, at a resolution of 0.32 °C. These characteristics make the circuit attractive for high-density thermal sensing.