Jammala Venkataramanaiah

This article describes the design of a fully fault-tolerant inverter configuration specifically for grid-connected and constant speed drive applications. The approach focuses on maintaining fault tolerance without increasing the device count in existing isolated configurations. The proposed topology employs a common cell and standard cells, each divided into operational and redundant half-bridge legs. Under normal operating conditions, the output voltage generates from operational legs. But, in the event of a switch fault, the corresponding switch in the redundant leg activates and replacing the fault switch. Besides, the proposed fault-tolerant control scheme operates within a single fundamental cycle of the output voltage waveform. During this cycle, each switch undergoes four rounds of scrutiny before any isolation occurs which significantly reducing the chances of misidentifying faults or triggering gate misfires. The fault detection and response are managed using only two output sensors (one for voltage and one for current), which streamlines the system and enhances its efficiency. The article includes a comparative study that demonstrates the effectiveness and practicality of this fault-tolerant approach compared to similar topologies and techniques. The proposed fault-tolerant topology and method will be validated through MATLAB Simulink simulations and confirmed with a hardware prototype.

Summary: In general, cascaded H‐bridge multilevel inverters (CHB‐MLI) are typically operated with either symmetrical or asymmetrical input DC sources, set at predefined specific ratios such as binary (1:2) or trinary (1:3) in the case of asymmetry, to achieve the desired output voltage waveform. However, if any DC source fails to provide the predefined voltage magnitude, or CHB‐MLIs with unspecified DC source ratios are utilized, the output voltage waveform may exhibit unequal magnitudes between consecutive levels, thereby causing a significant increase in total harmonic distortion (THD). Conventionally, to mitigate this effect, the corresponding H‐bridge is bypassed through zero voltage switching, which leads to an additional burden on the remaining H‐bridges to serve the same load. To reduce the burden on the remaining cells and improve the THD profile of the inverter, this article proposes a novel method for CHB‐MLI with varying DC magnitudes. It aims to enhance the quality of the output voltage waveform by strategically selecting optimum voltage levels rather than utilizing all available levels when CHB‐MLI has unspecified or variable DC sources. This approach can achieve a more balanced distribution of voltage magnitudes across successive levels by eliminating redundant states. Moreover, the proposed technique can reduce switch losses and enhance the converter's efficiency. The proposed method is validated through MATLAB/Simulink software simulations, followed by experimental verification.

Summary: A novel multilevel inverter (MLI) configuration with the hybrid switching technique is presented in this paper. The proposed MLI consists of the H‐bridge combination with unidirectional switches, half‐bridges, and transformers. The suggested MLI with the additional cascaded connection increases to higher voltage levels. The number of employed components in this topology is drastically minimized. Therefore, the complexity, cost, and volume of the proposed topology are also reduced. The operation of the suggested topology is tested through the improved novel switching technique. This modulation method reduces the total harmonic distortion (THD) and produces high root mean square (RMS) voltage. Further, a comprehensive comparison with the recent MLI topologies is performed to validate the merits of the suggested inverter. Simulation and experimental results verify the suggested topology performance using the new modulation technique at different loading conditions and modulation indices.

Nowadays, output voltage boosting gain property along with curtailment in the circuit voltage stress, and component count are considered as the essential topological features for the new multilevel inverter (MLI) circuits. Recognizing the above, a hybrid nine-level inverter topology (HNIT) for DC-AC conversion is proposed in this work. Each phase of the HNIT is designed with only eight semiconductor switches, one diode, and two electrolytic capacitors. Herein, series-parallel and conventional-series techniques are utilized effectively to balance the capacitor voltages. Further, cost and quantitative comparisons are carried among the state-of-art circuits to highlight the supremacy of proposed circuit. Subsequently, the performance of HNIT is verified experimentally with the fundamental switching PWM technique at different load conditions.

In this study, a novel nine‐level modified T‐type multilevel inverter (MT‐MLI) with a simple capacitor balancing technique is proposed. The proposed MT‐MLI circuit can generate higher levels with a single DC source and the minimum number of switching components. Each phase of the proposed topology contains ten switches and one flying capacitor (FC). The DC source voltage is divided into two parts with the help of capacitors. Phase disposition‐sine pulse‐width modulation technique is employed to regulate the DC‐link capacitors and FC voltages. To reduce the control complexity of FC‐based circuits, quarter‐cycle selector is introduced to control the FC voltage within the given half fundamental cycle using redundant states, so an external capacitor charging setup is not required. Furthermore, to highlight the potential merits of the proposed MT‐MLI, the comparison is made among state‐of‐the‐art MLIs. Simulation verification of the MT‐MLI is done using MATLAB/Simulink, and then hardware verifications are done using the laboratory prototype setup with Opal‐RT controller. Finally, adequate results are presented to validate the proposed MT‐MLI.

In this paper, a unusual switching technique is implemented using a fuzzy logic approach. The proposed technique simplifies the conventional method by eliminating the traditional logic gate design. The fuzzy logic pulse generator acts as a look-up table as well as a pulse generator. Based on the modulation index as input, controlled membership functions (MFs) and rules of the fuzzy logic controller (FLC) opens various possibilities in producing pulses directly. The proposed technique is evaluated on the cascaded multilevel inverter with symmetric and asymmetric operations using selective harmonic elimination pulse width modulation (SHE-PWM). MFs are designed based on the pre-calculated firing conditions for different modulation index values. The hardware verification is carried out to support the proposed switching technique.

This letter presents a single phase cascaded transformer multilevel inverter with modified carrier based level shift sinusoidal pulse width modulation (LS-SPWM) technique. The developed topology has two bridges with individual low frequency transformers. The bridges can generate quasi-square waveform and pulse width modulated (PWM) waveform independently and energized the two transformers whose secondary terminals are cascaded to attain nineteen level output voltage waveform across the load. The anticipated configuration has the least number of components to reduce the cost and enhance the reliability of the converter for medium power applications with inbuilt isolation. Furthermore, this paper presents the most common LS-SPWM technique with a new carrier to enhance the fundamental magnitude and shifts the dominant harmonics into three times of the traditional strategy for the same modulation indices. The performance of the proposed topology is validated with experimental results.

In this article, a novel cascaded transformer based multilevel inverter is presented for single phase systems. The proposed topology can produce a 19-level output waveform with fewer count parts. It consists of two bridges with individual low-frequency transformers. The bridges can generate quasi-square waveform and pulse width modulated (PWM) waveform independently and energized the two transformers whose secondary terminals are cascaded to attain the maximum number of levels in the output voltage waveform. Presence of the transformer in the configuration mainly provides the inbuilt isolation between the supply and load, higher order harmonics are filtered out due to the leakage inductance of the transformers and ratings of the power electronic switches are reduced since the transformers are boosted up the voltages. As per switching concerns, this paper presents the most common LS-SPWM technique with a new carrier to improves the fundamental magnitude and shifts the dominant harmonics into three times of the traditional strategy for the same modulation indices. The detailed loss analysis of the converter is also presented. The performance of the proposed topology is validated with MATLAB-Simulink software.

This paper presents a single phase 19-level inverter with less number of switching components, leading to reduce the cost and enhance reliability for renewable applications. The anticipated multilevel inverter has two bridges generate quasi-square and seven level uneven waveforms with an equal magnitude steps. Two voltage waveforms are cascaded at secondary side of transformers to create nineteen level output voltage waveform. Further, to find the appropriate switching instants of the proposed configuration, a new fundamental switching method named as fundamental sine quantized switching technique (FSQST) is presented. In fact, it has the capacity to provide N number of switching instants with less computational efforts, and attains optimized Total Harmonic Distortion (THD) in the output voltage. Finally, performance of the proposed topology is validated with simulations and hardware setup.