MSMarc Sanquer

Marc Sanquer

*This is an algorithmically generated author record based on publicly available information.

Current Organizations / Institutes

The organizations/institutes from the scholar's latest article


Marc Sanquer has a total of 181 co-authors. Here are the top co-authors by number of shared publications:


Latest Publications

  • Open Access

    Gate reflectometry of single-electron box arrays using calibrated low temperature matching networks

    by Matthew J. Filmer, Matthew Huebner, Thomas A. Zirkle, Xavier Jehl, Marc Sanquer, Jonathan D. Chisum, Alexei O. Orlov, Gregory L. Snider

    Sensitive dispersive readouts of single-electron devices (“gate reflectometry”) rely on one-port radio-frequency (RF) reflectometry to read out the state of the sensor. A standard practice in reflectometry measurements is to design an impedance transformer to match the impedance of the load to the characteristic impedance of the transmission line and thus obtain the best sensitivity and signal-to-noise ratio. This is particularly important for measuring large impedances, typical for dispersive readouts of single-electron devices because even a small mismatch will cause a strong signal degradation. When performing RF measurements, a calibration and error correction of the measurement apparatus must be performed in order to remove errors caused by unavoidable non-idealities of the measurement system. Lack of calibration makes optimizing a matching network difficult and ambiguous, and it also prevents a direct quantitative comparison between measurements taken of different devices or on different systems. We propose and demonstrate a simple straightforward method to design and optimize a pi matching network for readouts of devices with large impedance, \(Z \ge 1\hbox {M}\Omega\). It is based on a single low temperature calibrated measurement of an unadjusted network composed of a single L-section followed by a simple calculation to determine a value of the “balancing” capacitor needed to achieve matching conditions for a pi network. We demonstrate that the proposed calibration/error correction technique can be directly applied at low temperature using inexpensive calibration standards. Using proper modeling of the matching networks adjusted for low temperature operation the measurement system can be easily optimized to achieve the best conditions for energy transfer and targeted bandwidth, and can be used for quantitative measurements of the device impedance. In this work we use gate reflectometry to readout the signal generated by arrays of parallel-connected Al-AlOx single-electron boxes. Such arrays can be used as a fast nanoscale voltage sensor for scanning probe applications. We perform measurements of sensitivity and bandwidth for various settings of the matching network connected to arrays and obtain strong agreement with the simulations.


  • Dispersive vs charge-sensing readout for linear quantum registers

    by A. Apra, A. Crippa, M. L. V. Tagliaferri, J. Li, R. Ezzouch, B. Bertrand, L. Hutin, N. Rambal, E. Catapano, H. Niebojewsky, et al.

    We present recent progress in the implementation of scalable schemes for spin qubit readout in one dimensional quantum registers based on fully-depleted silicon-on-insulator (FDSOI) technology. We compare two schemes both based on rf gate reflectometry. The first one, denoted as dispersive readout, minimizes the device overhead thereby facilitating scale-up to large qubit registers. The second one, denoted as charge-sensing readout, requires additional readout components but is less sensitive to the strength of the interdot coupling facilitating operation in the few-electron regime. We demonstrate single-shot charge sensing with a fidelity of 97% in 5 μs. Finally, we propose a scalable device architecture for linear qubit registers relying on charge-sensing readout.


  • Open Access

    Radio Frequency Reflectometry of Single-Electron Box Arrays for Nanoscale Voltage Sensing Applications

    by Thomas A. Zirkle, Matthew J. Filmer, Jonathan Chisum, Alexei O. Orlov, Eva Dupont-Ferrier, Joffrey Rivard, Matthew Huebner, Marc Sanquer, Xavier Jehl, Gregory L. Snider

    Single-electron tunneling transistors (SETs) and boxes (SEBs) exploit the phenomenon of Coulomb blockade to achieve unprecedented charge sensitivities. Single-electron boxes, however, despite their simplicity compared to SETs, have rarely been used for practical applications. The main reason for that is that unlike a SET where the gate voltage controls conductance between the source and the drain, an SEB is a two terminal device that requires either an integrated SET amplifier or high-frequency probing of its complex admittance by means of radio frequency reflectometry (RFR). The signal to noise ratio (SNR) for a SEB is small, due to its much lower admittance compared to a SET and thus matching networks are required for efficient coupling ofSEBs to an RFR setup. To boost the signal strength by a factor of N (due to a random offset charge) SEBs can be connected in parallel to form arrays sharing common gates and sources. The smaller the size of the SEB, the larger the charging energy of a SEB enabling higher operation temperature, and using devices with a small footprint (1000) can be assembled into an array occupying just a few square microns. We show that it is possible to design SEB arrays that may compete with an SET in terms of sensitivity. In this, we tested SETs using RF reflectometry in a configuration with no DC through path (“DC-decoupled SET” or DCD SET) along with SEBs connected to the same matching network. The experiment shows that the lack of a path for a DC current makes SEBs and DCD SETs highly electrostatic discharge (ESD) tolerant, a very desirable feature for applications. We perform a detailed analysis of experimental data on SEB arrays of various sizes and compare it with simulations to devise several ways for practical applications of SEB arrays and DCD SETs.


  • Open Access

    Low-power transimpedance amplifier for cryogenic integration with quantum devices

    by L. Le Guevel, G. Billiot, B. Cardoso Paz, M. L. V. Tagliaferri, S. De Franceschi, R. Maurand, M. Cassé, M. Zurita, M. Sanquer, M. Vinet, et al.

    The development of quantum electronic devices operating below a few Kelvin degrees is raising the demand for cryogenic complementary metal-oxide-semiconductor electronics (CMOS) to be used as in situ classical control/readout circuitry. Having a minimal spatial separation between quantum and classical hardware is necessary to limit the electrical wiring to room temperature and the associated heat load and parasitic capacitances. Here, we report prototypical demonstrations of hybrid circuits combining silicon quantum dot devices and a classical transimpedance amplifier, which is characterized and then used to measure the current through the quantum dots. The two devices are positioned next to each other at 4.2 K to assess the use of the cryogenic transimpedance amplifier with respect to a room-temperature transimpedance amplifier. A quantum device built on the same substrate as the transimpedance amplifier is characterized down to 10 mK. The transimpedance amplifier is based on commercial 28 nm fully depleted Silicon-on-insulator (FDSOI) CMOS. It consists of a two-stage Miller-compensated operational amplifier with a 10 MΩ polysilicon feedback resistor, yielding a gain of 1.1 × 10 7 V/A. We show that the transimpedance amplifier operates at 10 mK with only 1 μW of power consumption, low enough to prevent heating. It exhibits linear response up to ±40 nA and a measurement bandwidth of 2.6 kHz, which could be extended to about 200 kHz by design optimization. The realization of custom-made electronics in FDSOI technology for cryogenic operation at any temperature will improve measurement speed and quality inside cryostats with higher bandwidth, lower noise, and higher signal-to-noise ratio.


  • Open Access

    Charge Detection in an Array of CMOS Quantum Dots

    by Emmanuel Chanrion, David J. Niegemann, Benoit Bertrand, Cameron Spence, Baptiste Jadot, Jing Li, Pierre-André Mortemousque, Louis Hutin, Romain Maurand, Xavier Jehl, et al.

    The recent development of arrays of quantum dots in semiconductor nanostructures highlights the progress of quantum devices toward a large scale. However, how to realize such arrays on a scalable platform such as silicon is still an open question. One of the main challenges lies in the detection of charges within the array. It is a prerequisite to initialize a desired charge state and read out spins through spin-to-charge conversion mechanisms. In this work, we use two methods based on either a single-lead charge detector or a reprogrammable single-electron transistor. By these methods, we study the charge dynamics and sensitivity by performing single-shot detection of the charge. Finally, we can probe the charge stability at any node of a linear array and assess the Coulomb disorder in the structure. We find an electrochemical potential fluctuation induced by charge noise comparable to that reported in other silicon quantum dots.


  • Top Cited Papers

    Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening

    by H. Bohuslavskyi, A. G. M. Jansen, S. Barraud, V. Barral, M. Casse, L. Le Guevel, X. Jehl, L. Hutin, B. Bertrand, G. Billiot, et al.


  • All-Electrical Control of a Hybrid Electron Spin/Valley Quantum Bit in SOI CMOS Technology

    by Leo Bourdet, Louis Hutin, Benoit Bertrand, Andrea Corna, Heorhii Bohuslavskyi, Anthony Amisse, Alessandro Crippa, Romain Maurand, Sylvain Barraud, Matias Urdampilleta, et al.

    We fabricated quantum dot devices using a standard SOI CMOS process flow and demonstrated that the spin of confined electrons could be controlled via a local electrical-field excitation, owing to intervalley spin–orbit coupling. We discuss that modulating the confinement geometry via an additional electrode may enable switching a quantum bit (qubit) between an electrically addressable valley configuration and a protected spin configuration. This proposed scheme bears relevance to improve the tradeoff between fast operations and slow decoherence for quantum computing on a Si qubit platform. Finally, we evoke the impact of process-induced variability on the operating bias range.


  • Open Access

    Electrically driven electron spin resonance mediated by spin–valley–orbit coupling in a silicon quantum dot

    by Andrea Corna, Léo Bourdet, Romain Maurand, Alessandro Crippa, Dharmraj Kotekar-Patil, Heorhii Bohuslavskyi, Romain Laviéville, Louis Hutin, Sylvain Barraud, Xavier Jehl, et al.

    The ability to manipulate electron spins with voltage-dependent electric fields is key to the operation of quantum spintronics devices, such as spin-based semiconductor qubits. A natural approach to electrical spin control exploits the spin–orbit coupling (SOC) inherently present in all materials. So far, this approach could not be applied to electrons in silicon, due to their extremely weak SOC. Here we report an experimental realization of electrically driven electron–spin resonance in a silicon-on-insulator (SOI) nanowire quantum dot device. The underlying driving mechanism results from an interplay between SOC and the multi-valley structure of the silicon conduction band, which is enhanced in the investigated nanowire geometry. We present a simple model capturing the essential physics and use tight-binding simulations for a more quantitative analysis. We discuss the relevance of our findings to the development of compact and scalable electron–spin qubits in silicon.


  • SOI CMOS technology for quantum information processing

    by L. Hutin, B. Bertrand, R. Maurand, M. Urdampilleta, B. Jadot, H. Bohuslavskyi, L. Bourdet, Y.-M. Niquet, X. Jehl, S. Barraud, et al.

    We present some recent progress towards the implementation of semiconductor spin quantum bits derived from a Si CMOS technology platform. Our approach consists in developing a foundry-compatible embodiment of the basic building block of quantum information, with a strong potential for large scale co-integration of a quantum core with its mandatory classical control and readout electronics. After introducing various qubit manipulation, coupling and readout schemes, we discuss some prospects for scalability, and in particular some potential advantages of the FDSOI technology.


  • Open Access

    Development of a CMOS Route for Electron Pumps to Be Used in Quantum Metrology

    by Sylvain Barraud, Romain Lavieville, Louis Hutin, Heorhii Bohuslavskyi, Maud Vinet, Andrea Corna, Paul Clapera, Marc Sanquer, Xavier Jehl

    The definition of the ampere will change in the next few years. This electrical base unit of the S.I. will be redefined by fixing the value of the charge quantum, i.e., the electron charge e. As a result electron pumps will become the natural device for the mise en pratique of this new ampere. In the last years semiconductor electron pumps have emerged as the most advanced systems, both in terms of speed and precision. Another figure of merit for a metrological device would be its ability to be predictible and shared. For that reason a mature fabrication process would certainly be an advantage. In this article we present electron pumps made within a CMOS (Complementary Metal Oxide Semiconductor) research facility on 300 mm silicon-on-insulator wafers, using advanced microelectronics tools and processes. We give an overview of the whole integration scheme and emphasize the fabrication steps which differ from the normal CMOS route.