Jiang Nan
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Jiang Nan has a total of 35 co-authors. Here are the top co-authors by number of shared publications:
Youguang Zhang
Fert Beijing Institute, School of Microelectronics, BDBC, Beihang University, Beijing, 100191, China
4 shared publicationsWeisheng Zhao
3 shared publications- Yue Zhang
Fert Beijing Institute, School of Integrated Circuit Science and Engineering, Beihang University 1 , Beijing 100191
3 shared publications Zhizhong Zhang
Fert Beijing Institute, School of Microelectronics, BDBC, Beihang University, Beijing, 100191, China
3 shared publicationsGuanda Wang
Fert Beijing Institute, School of Microelectronics, BDBC, Beihang University, Beijing, 100191, China
2 shared publicationsKun Zhang
Fert Beijing Institute, School of Microelectronics, BDBC, Beihang University, Beijing, 100191, China
2 shared publications
Latest Publications
- 13 April 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 41 (6) , 928-931
Rectified Tunnel Magnetoresistance Device With High On/Off Ratio for In-Memory Computing
Low on/off ratio gravely hinders the application of magnetoresistance (MR) devices for the accurate and reliable data fetch. In this paper, a rectified tunnel MR (R-TMR) device is fabricated by integrating perpendicular-magnetic-anisotropy magnetic tunnel junction (PMA MTJ) and Schottky diode. High on/off ratio, intrinsic non-volatility and multi-dimensional regulation capabilities can be obtained, which makes this emerging spintronic device suitable for in-memory computing (IMC). By reversing the rectifying direction of the diode and tuning the proportions of alternating current (AC) and direct current (DC), reconfigurable logic operations have been achieved. Two proofs of concept, i.e. “NOR” and “NAND”, are experimentally performed.
- 13 April 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 41 (6) , 928-931
Rectified Tunnel Magnetoresistance Device With High On/Off Ratio for In-Memory Computing
Low on/off ratio gravely hinders the application of magnetoresistance (MR) devices for the accurate and reliable data fetch. In this paper, a rectified tunnel MR (R-TMR) device is fabricated by integrating perpendicular-magnetic-anisotropy magnetic tunnel junction (PMA MTJ) and Schottky diode. High on/off ratio, intrinsic non-volatility and multi-dimensional regulation capabilities can be obtained, which makes this emerging spintronic device suitable for in-memory computing (IMC). By reversing the rectifying direction of the diode and tuning the proportions of alternating current (AC) and direct current (DC), reconfigurable logic operations have been achieved. Two proofs of concept, i.e. “NOR” and “NAND”, are experimentally performed.
- 10 October 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 40 (12) , 1984-1987
Skyrmion-Based Ultra-Low Power Electric-Field-Controlled Reconfigurable (SUPER) Logic Gate
- 10 October 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 40 (12) , 1984-1987
Skyrmion-Based Ultra-Low Power Electric-Field-Controlled Reconfigurable (SUPER) Logic Gate
- 11 September 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 66 (1) , 215-225
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design
Information storage and transfer via current-induced domain wall (DW) motions exhibit significant density-speed-energy advantages, which inspires numerous emerging devices and circuits, such as racetrack memory (RM). However, the bi-directional propagation of DWs in the conventional tape-shaped nanowire will lead to data overflow issue, implicitly deteriorating storage density and operational performances. In this paper, we propose a non-volatile cache design based on spin-orbit torque-driven ring-shaped RM. The systematical investigations, covering from device modeling, to circuits design, to bit-cell layout design, and to system evaluation have been carried out. Thanks to the cells-overlapping design, the proposed RM L2 cache can achieve 48×, 16×, and 8× improvements in term of capacity, compared with iso-area caches based on static random access memory (SRAM), spin transfer torque magnetic RAM (STT-MRAM), and tape-shaped RM, respectively. As proved by 4-core system experiment results, the proposed RM cache can improve 30.7% instructions per cycle (IPC) and save 58.2% energy compared with SRAM cache.
- 11 September 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 66 (1) , 215-225
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design
Information storage and transfer via current-induced domain wall (DW) motions exhibit significant density-speed-energy advantages, which inspires numerous emerging devices and circuits, such as racetrack memory (RM). However, the bi-directional propagation of DWs in the conventional tape-shaped nanowire will lead to data overflow issue, implicitly deteriorating storage density and operational performances. In this paper, we propose a non-volatile cache design based on spin-orbit torque-driven ring-shaped RM. The systematical investigations, covering from device modeling, to circuits design, to bit-cell layout design, and to system evaluation have been carried out. Thanks to the cells-overlapping design, the proposed RM L2 cache can achieve 48×, 16×, and 8× improvements in term of capacity, compared with iso-area caches based on static random access memory (SRAM), spin transfer torque magnetic RAM (STT-MRAM), and tape-shaped RM, respectively. As proved by 4-core system experiment results, the proposed RM cache can improve 30.7% instructions per cycle (IPC) and save 58.2% energy compared with SRAM cache.
- 7 September 2018
- Published by Springer Nature in Journal of Materials Science: Materials in Electronics
- Vol. 29 (21) , 18476-18485
Effect of phosphor composition and packaging structure of flexible phosphor films on performance of white LEDs
- 7 September 2018
- Published by Springer Nature in Journal of Materials Science: Materials in Electronics
- Vol. 29 (21) , 18476-18485
Effect of phosphor composition and packaging structure of flexible phosphor films on performance of white LEDs
- 13 October 2016
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-2
Performance evaluation and optimization of single layer MoS2 double gate transistors with metallic contacts
In this work, the performance of single layer MoS2 double gate transistors with metallic contacts is evaluated with quantum ballistic calculation. The image force which is crucial for accurate simulation of Schottky barrier is taken into account. The simulation results reveal that increasing doping concentration is the most effective way to adjust transistor performance, and device performance of transistors with metallic contacts can be comparable and even outperforms that with ohmic contacts.
- 13 October 2016
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-2
Performance evaluation and optimization of single layer MoS2 double gate transistors with metallic contacts
In this work, the performance of single layer MoS2 double gate transistors with metallic contacts is evaluated with quantum ballistic calculation. The image force which is crucial for accurate simulation of Schottky barrier is taken into account. The simulation results reveal that increasing doping concentration is the most effective way to adjust transistor performance, and device performance of transistors with metallic contacts can be comparable and even outperforms that with ohmic contacts.