Jianguo Yang

The imprint effect, a major reliability issue in ferroelectric memories, degrades the device by shifting the coercive field over time. This work reviews existing imprint models and introduces a phase-field model for polycrystalline thin films. The model identifies grain-boundary charge screening (GBCS) as a key bulk imprint mechanism. It demonstrates that the depolarization field near grain boundaries attracts trapped charges, which in turn suppress domain nucleation for reverse polarization switching. Furthermore, the model reveals that domain wall motion is essential for the GBCS mechanism to induce imprint in a thin film and can explain the widened hysteresis loop observed in experiments. These findings provide new insights into imprint physics and advance strategies for improving ferroelectric memory reliability.

Antiferroelectric (AFE) materials are promising for various applications in electronic devices and energy‐related systems. While the switching mechanisms of ferroelectric (FE) materials have been extensively studied, those of AFE materials still require substantial investigation. Here, we investigate the switching mechanism in hafnia‐based AFE capacitors by probing the bias‐dependent evolution of their double‐loop polarization–voltage hysteresis. We systematically track the voltage shifts of the four current peaks in the double‐loop hysteresis as functions of set voltage and stress time. We observe two distinct features: a threshold‐activated voltage shift of the switching current peaks and a polarity‐selective narrowing of the hysteresis sub‐loops. While a conventional uniform charge screening model accounts for the first feature, it fails to capture the second. The subtle disparities in the evolution of the four current peaks are instead captured by a phase‐field model that incorporates domain nucleation and domain wall motion with localized imprint. This work clarifies the switching mechanisms in AFE capacitors and suggests device applications grounded in this mechanistic understanding.

This paper presents an energy-efficient spike-sorting system-on-chip (SoC) designed for closed-loop brain-computer interfaces of massive probing channels. The design first incorporates a sparsity/similarity-aware spike detection scratchpad, leveraging a bit-wise differential encoder and zero-friendly read-out circuits, reducing the dynamic power consumption of spike detection by 77.7%. To mitigate static power dissipation, it also introduces an ultra-low-leakage dual-voltage 5T-SRAM array with level-shifter embedded sense amplifiers, achieving an 82.2% leakage power reduction of neural signal buffering by applying half $V_{DD}$ on SRAM cells. Additionally, a memory hierarchy architecture combining on-chip SRAM and off-chip FeRAM, along with a firing-rate-based Osort for cluster template management, minimizes off-chip memory access to only 9.7% with a latency of $11.7\mu $ s for 1024-channel spike sorting. A silicon prototype is fabricated in 28-nm CMOS technology, which achieves a power consumption of 583nW/channel and an area consumption of 0.0012mm²/channel. The chip supports real-time spike sorting with up to 16K templates, $21.3\times $ greater than the state-of-the-art spike-sorting processor.

Designing computing-in-memory (CIM) chips with synaptic plasticity can potentially support energy-efficient on-chip learning in edge devices for rapid local task adaptation. Its silicon implementation is challenging as it requires hybridizing nonvolatile and volatile memory (VM) and customized computational operations. In this work, we propose a plastic CIM (P-CIM) macro featuring: 1) the logic-compatible flash (LF) cells in a standard 14-nm logic process that can be integrated with static random access memory (SRAM) cells in the same array; 2) the plastic cell array (PCA) that can perform matrix elementwise multiplication (MEM) followed by matrix-vector multiplication (MVM) in a single clock cycle; 3) the differential merged-into-array analog-to-digital converter (DMA-ADC) with capacitor reuse and a multielement sparsity-aware (MESA) scheme to reduce area and power consumption. A P-CIM macro integrating 32 k LF cells, 4 k SRAM cells, and 32 8-bit DMA-ADCs is fabricated in a 14-nm FinFET logic process. It achieves a peak energy efficiency (EF) of 22.64 TOPS/W for the MEM-MVM operations. It achieves computing accuracies of 78.04% on the Omniglot one-shot learning task and 89.65% on the CIFAR-10 pattern memorization task.

Edge artificial intelligence systems require higher frequency due to intensive computational demands, while most traditional entropy sources decay with frequency. This work shows the physical properties of the Fe-diode devices are ideal for edge systems with high frequencies and dramatic temperature changes. The noise density of Fe-diode can be modified by the amplitude of the read voltage and remains stable at high frequencies and temperature fluctuations. A Bayesian neural network with Fe-diode devices is experimentally implemented in high-speed, high-density silicon-based chips. This hierarchical Bayesian neural network is demonstrated on 3D 16-layer Fe-diode array based on unified entropy source and 4-state synapse. Properties including high area efficiency, wide working temperature range, low energy in-situ training, high recognition accuracy are finally achieved.