Zhengwei Qi
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Zhengwei Qi has a total of 213 co-authors. Here are the top co-authors by number of shared publications:
- Yun Wang
Shanghai Jiao Tong University
23 shared publications - Haibing Guan
Shanghai Jiao Tong University, Shanghai, China
16 shared publications Haibing Guan
13 shared publications- Chen Chen
Shanghai Jiao Tong University
10 shared publications - James Yen
Shanghai Jiao Tong University
9 shared publications - Zhibai Huang
Shanghai Jiao Tong University
8 shared publications
Latest Publications
- 1 December 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Mobile Computing
- Vol. 25 (12) , 22457-22473
RISCing It All: Accelerating Binary Translation Using Software-Only Validated Flag Speculation
- 1 December 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Mobile Computing
- Vol. 25 (12) , 22457-22473
RISCing It All: Accelerating Binary Translation Using Software-Only Validated Flag Speculation
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 45 (11) , 6091-6104
DevTrace: Lightweight Plug-In Design for PCIe Transaction Tracing in Edge Intelligence Workloads
Tracing host–peripheral interactions is essential for optimizing edge and latency-sensitive systems, yet existing non-invasive MMIO tracing can impose prohibitive overhead under load. We present DevTrace, a low-overhead tracing framework that records semantically stable control-plane boundary events (e.g., submission, receive aggregation, interrupt entry) together with derived data-plane metrics (e.g., bytes, direction, identifiers such as queue/vector ids when available, and timestamps). Dev- Trace uses lightweight driver-level reporting stubs, a contention-optimized ring buffer, and a user-space handler that performs heavy correlation and analysis, yielding an OS-feature-light design that applies to both kernel- and user-space driver stacks. In NIC micro-benchmarks, DevTrace achieves lossless capture with 8KB buffers (50 ms polling) and 0.6–2.6% CPU overhead, whereas MMIOtrace requires up to 4–8MB buffers and 22–31% CPU overhead. In end-to-end macro-benchmarks co-locating Nginx with six model inference workloads, DevTrace keeps HTTP-serving p99 latency inflation within ∼6% and throughput degradation within 35%; inference slowdown is single-digit for Stable Diffusion workloads and generally within the tens of percent for the remaining models (with one outlier under r8169). In contrast, page-fault-based tracing can collapse co-located performance, degrading inference by over 200% and increasing p99 latency by over 500% in our settings.We further demonstrate portability via a Zephyr RTOS port and a user-space Vulkan-layer integration on QNX, and show that a Rust implementation of the core ring buffer incurs no meaningful runtime performance penalty.
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 45 (11) , 6091-6104
DevTrace: Lightweight Plug-In Design for PCIe Transaction Tracing in Edge Intelligence Workloads
Tracing host–peripheral interactions is essential for optimizing edge and latency-sensitive systems, yet existing non-invasive MMIO tracing can impose prohibitive overhead under load. We present DevTrace, a low-overhead tracing framework that records semantically stable control-plane boundary events (e.g., submission, receive aggregation, interrupt entry) together with derived data-plane metrics (e.g., bytes, direction, identifiers such as queue/vector ids when available, and timestamps). Dev- Trace uses lightweight driver-level reporting stubs, a contention-optimized ring buffer, and a user-space handler that performs heavy correlation and analysis, yielding an OS-feature-light design that applies to both kernel- and user-space driver stacks. In NIC micro-benchmarks, DevTrace achieves lossless capture with 8KB buffers (50 ms polling) and 0.6–2.6% CPU overhead, whereas MMIOtrace requires up to 4–8MB buffers and 22–31% CPU overhead. In end-to-end macro-benchmarks co-locating Nginx with six model inference workloads, DevTrace keeps HTTP-serving p99 latency inflation within ∼6% and throughput degradation within 35%; inference slowdown is single-digit for Stable Diffusion workloads and generally within the tens of percent for the remaining models (with one outlier under r8169). In contrast, page-fault-based tracing can collapse co-located performance, degrading inference by over 200% and increasing p99 latency by over 500% in our settings.We further demonstrate portability via a Zephyr RTOS port and a user-space Vulkan-layer integration on QNX, and show that a Rust implementation of the core ring buffer incurs no meaningful runtime performance penalty.
- Open Access
- 26 October 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
vMiG: A Fast and NUMA-Aware Virtualized GPU Migration System via Pipelined Zero-Copy Data Paths
GPUs have become indispensable infrastructure for cloud platforms, powering workloads from large-model inference to real-time rendering, and the transition to cloud-native GPU computing is accelerating. One of the key challenges in this transition is live migration, which is essential for enabling transparent workload relocation for load balancing, fault tolerance, and resource consolidation. However, GPU virtualization introduces a critical migration bottleneck rooted in the mediated pass-through (MPT) migration stack: massive device state, particularly VRAM footprints scaling into tens of gigabytes, must be exported through vendor-controlled interfaces whose buffering, copying, and placement behavior limits high-throughput VRAM streaming in practice. To address this challenge, we propose vMiG , a framework that first characterizes why the MPT migration data path is poorly matched to high-throughput VRAM streaming. vMiG then uses this analysis to restructure the migration pipeline for higher VRAM transfer throughput and shorter blackout time, through zero-copy data movement, end-to-end pipelining, and non-uniform memory access (NUMA)-aware control path placement. Evaluations show that NUMA-aware controller placement improves VRAM migration throughput by 58.8%, while copy-path optimizations reduce memory copies from seven to near the theoretical minimum of four. Together, these optimizations achieve VRAM migration throughput up to 5.19 × the baseline rate and reduce end-to-end migration time by up to 58% for VRAM-intensive AI workloads.
- 26 October 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
Open AccessvMiG: A Fast and NUMA-Aware Virtualized GPU Migration System via Pipelined Zero-Copy Data Paths
GPUs have become indispensable infrastructure for cloud platforms, powering workloads from large-model inference to real-time rendering, and the transition to cloud-native GPU computing is accelerating. One of the key challenges in this transition is live migration, which is essential for enabling transparent workload relocation for load balancing, fault tolerance, and resource consolidation. However, GPU virtualization introduces a critical migration bottleneck rooted in the mediated pass-through (MPT) migration stack: massive device state, particularly VRAM footprints scaling into tens of gigabytes, must be exported through vendor-controlled interfaces whose buffering, copying, and placement behavior limits high-throughput VRAM streaming in practice. To address this challenge, we propose vMiG , a framework that first characterizes why the MPT migration data path is poorly matched to high-throughput VRAM streaming. vMiG then uses this analysis to restructure the migration pipeline for higher VRAM transfer throughput and shorter blackout time, through zero-copy data movement, end-to-end pipelining, and non-uniform memory access (NUMA)-aware control path placement. Evaluations show that NUMA-aware controller placement improves VRAM migration throughput by 58.8%, while copy-path optimizations reduce memory copies from seven to near the theoretical minimum of four. Together, these optimizations achieve VRAM migration throughput up to 5.19 × the baseline rate and reduce end-to-end migration time by up to 58% for VRAM-intensive AI workloads.
- Open Access
- 19 October 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
DMMU: SmartNIC-Based On-Device MMU for Scalable Virtualized I/O and Memory Overcommitment
Cloud data centers increasingly rely on device virtualization to share high-bandwidth network adapters and accelerators among virtual machines (VMs). Single Root I/O Virtualization (SR-IOV) exposes Virtual Functions (VFs) directly to guest VMs, but the Input/Output Memory Management Unit (IOMMU) on the host processor becomes a bottleneck as the number of VFs grows: its small translation lookaside buffer (TLB) causes severe throughput degradation. Meanwhile, because the hypervisor cannot determine which guest memory regions are used for Direct Memory Access (DMA), it must pin the entire VM memory, preventing memory overcommitment and wasting physical resources. Existing solutions, including Address Translation Services (ATS), the Page Request Interface (PRI), and software-emulated virtual IOMMUs, suffer from compatibility, deployment, or CPU overhead limitations. We propose DMMU, a Device MMU system implemented on programmable SmartNICs that addresses both the IOMMU translation bottleneck and the memory-pinning barrier to overcommitment, with minimal host software modification and zero guest awareness. DMMU introduces two techniques: combo-DMA , which dynamically routes address translations between the IOMMU and an on-device translation engine depending on IOMMU load, and direct-PRI , which enables the SmartNIC to issue page fault requests directly to a host-side driver, bypassing the multi-layer emulation path of conventional PRI in virtualized environments. We implement DMMU through a microcode update to a commodity dual-port 100G NIC and evaluate it on Intel Skylake and Ice Lake servers. With a representative 120-VF configuration, DMMU improves NIC throughput by 65% and reduces IOTLB misses by 38 × compared to the baseline IOMMU. DMMU also enables reliable memory overcommitment with device passthrough, achieving near-baseline Redis performance at a 1.35 × overcommitment ratio.
- 19 October 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
Open AccessDMMU: SmartNIC-Based On-Device MMU for Scalable Virtualized I/O and Memory Overcommitment
Cloud data centers increasingly rely on device virtualization to share high-bandwidth network adapters and accelerators among virtual machines (VMs). Single Root I/O Virtualization (SR-IOV) exposes Virtual Functions (VFs) directly to guest VMs, but the Input/Output Memory Management Unit (IOMMU) on the host processor becomes a bottleneck as the number of VFs grows: its small translation lookaside buffer (TLB) causes severe throughput degradation. Meanwhile, because the hypervisor cannot determine which guest memory regions are used for Direct Memory Access (DMA), it must pin the entire VM memory, preventing memory overcommitment and wasting physical resources. Existing solutions, including Address Translation Services (ATS), the Page Request Interface (PRI), and software-emulated virtual IOMMUs, suffer from compatibility, deployment, or CPU overhead limitations. We propose DMMU, a Device MMU system implemented on programmable SmartNICs that addresses both the IOMMU translation bottleneck and the memory-pinning barrier to overcommitment, with minimal host software modification and zero guest awareness. DMMU introduces two techniques: combo-DMA , which dynamically routes address translations between the IOMMU and an on-device translation engine depending on IOMMU load, and direct-PRI , which enables the SmartNIC to issue page fault requests directly to a host-side driver, bypassing the multi-layer emulation path of conventional PRI in virtualized environments. We implement DMMU through a microcode update to a commodity dual-port 100G NIC and evaluate it on Intel Skylake and Ice Lake servers. With a representative 120-VF configuration, DMMU improves NIC throughput by 65% and reduces IOTLB misses by 38 × compared to the baseline IOMMU. DMMU also enables reliable memory overcommitment with device passthrough, achieving near-baseline Redis performance at a 1.35 × overcommitment ratio.
- Open Access
- 13 October 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 23 (4) , 1-22
UniC: A Unified Automotive Cockpit Domain Management System for Enhanced In-vehicle Infotainment
Modern intelligent cockpits consolidate In-Vehicle Infotainment (IVI), navigation, and control-related services on shared heterogeneous hardware. This consolidation creates a resource-management problem because cockpit workloads have different controllability, safety, and performance requirements. Existing open-source cockpit-domain platforms either fix the hardware partition at design time or route IVI through para-virtualized I/O stacks that impose large rendering overheads. As a result, performance-sensitive IVI workloads cannot effectively use onboard GPUs even when safety-critical workloads do not need those resources. We present UniC , a unified cockpit-domain resource management system based on attribute-aware task placement. UniC models each workload through controllability, safety demand, and performance demand, and maps workloads to four execution environments through a piecewise assignment policy. UniC does not replace the underlying safety stack; it preserves hypervisor- and IOMMU-enforced boundaries for safety-critical workloads while avoiding over-provisioned isolation for low-safety infotainment tasks. For IVI, UniC realizes this placement through GPU passthrough, display synthesis acceleration, cross-platform application support, and optional nearby-edge rendering for passenger devices. In our prototype, UniC reduces normalized IVI virtualization overhead from 38.7% to 11.8% compared with the reproduced open-source AMD/Xen baseline, a 26.9-percentage-point reduction. UniC maintains hypervisor-level performance isolation across execution environments. Under controlled network impairment, in-vehicle edge rendering keeps on-screen response latency substantially more stable than a cloud-based alternative.
- 13 October 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 23 (4) , 1-22
Open AccessUniC: A Unified Automotive Cockpit Domain Management System for Enhanced In-vehicle Infotainment
Modern intelligent cockpits consolidate In-Vehicle Infotainment (IVI), navigation, and control-related services on shared heterogeneous hardware. This consolidation creates a resource-management problem because cockpit workloads have different controllability, safety, and performance requirements. Existing open-source cockpit-domain platforms either fix the hardware partition at design time or route IVI through para-virtualized I/O stacks that impose large rendering overheads. As a result, performance-sensitive IVI workloads cannot effectively use onboard GPUs even when safety-critical workloads do not need those resources. We present UniC , a unified cockpit-domain resource management system based on attribute-aware task placement. UniC models each workload through controllability, safety demand, and performance demand, and maps workloads to four execution environments through a piecewise assignment policy. UniC does not replace the underlying safety stack; it preserves hypervisor- and IOMMU-enforced boundaries for safety-critical workloads while avoiding over-provisioned isolation for low-safety infotainment tasks. For IVI, UniC realizes this placement through GPU passthrough, display synthesis acceleration, cross-platform application support, and optional nearby-edge rendering for passenger devices. In our prototype, UniC reduces normalized IVI virtualization overhead from 38.7% to 11.8% compared with the reproduced open-source AMD/Xen baseline, a 26.9-percentage-point reduction. UniC maintains hypervisor-level performance isolation across execution environments. Under controlled network impairment, in-vehicle edge rendering keeps on-screen response latency substantially more stable than a cloud-based alternative.
- 1 October 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Parallel and Distributed Systems
- Vol. 37 (10) , 2153-2164
gPooling: An Elastic GPU Resource Management Framework for On-Demand Virtualization in Shared Accelerator Clusters
- 1 October 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Parallel and Distributed Systems
- Vol. 37 (10) , 2153-2164
gPooling: An Elastic GPU Resource Management Framework for On-Demand Virtualization in Shared Accelerator Clusters
- Open Access
- 28 September 2026
- Published by Association for Computing Machinery (ACM)
- p. 516-532
You Can Always Get What You Want: CPU Virtualization Made Fast and Free
- 28 September 2026
- Published by Association for Computing Machinery (ACM)
- p. 516-532
Open AccessYou Can Always Get What You Want: CPU Virtualization Made Fast and Free
- 10 September 2026
- Published by Springer Nature
- p. 261-277
FedNASP: Federated Vision-Language Navigation with Adaptive Step-wise Personalization
- 10 September 2026
- Published by Springer Nature
- p. 261-277
FedNASP: Federated Vision-Language Navigation with Adaptive Step-wise Personalization
- Open Access
- 5 September 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 23 (4) , 1-21
CarDroid: Container-Based Architecture for Graphic-Intensive Tasks in Automotive Cockpits
The automotive industry has widely adopted GPUs for In-Vehicle Infotainment (IVI) systems, which support applications ranging from navigation to graphics-intensive gaming. However, current automotive GPU virtualization solutions often lack the efficiency, flexibility, and low overhead required in vehicle cockpits. Insufficient isolation under dynamic workloads can cause performance fluctuations and delays, including in latency-sensitive tasks such as route planning. To address these limitations, we introduce CarDroid, a GPU virtualization solution for in-vehicle systems. CarDroid has three main components: (1) a lightweight container runtime that offloads graphics tasks and minimizes interference, (2) cross-OS buffer projection that shares a rendering buffer with the Android host to eliminate redundant cross-OS copies, and (3) a PMU-guided predictor for real-time resource adjustment. Across the tested workload combinations, these mechanisms reduce the arithmetic-mean interference ratio by 31.83%, with a virtualization-overhead premium of 9.19 percentage points over a GPU-passthrough baseline. CarDroid was piloted and validated on production cockpit platforms across 10 vehicle models at 9 automotive companies.
- 5 September 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 23 (4) , 1-21
Open AccessCarDroid: Container-Based Architecture for Graphic-Intensive Tasks in Automotive Cockpits
The automotive industry has widely adopted GPUs for In-Vehicle Infotainment (IVI) systems, which support applications ranging from navigation to graphics-intensive gaming. However, current automotive GPU virtualization solutions often lack the efficiency, flexibility, and low overhead required in vehicle cockpits. Insufficient isolation under dynamic workloads can cause performance fluctuations and delays, including in latency-sensitive tasks such as route planning. To address these limitations, we introduce CarDroid, a GPU virtualization solution for in-vehicle systems. CarDroid has three main components: (1) a lightweight container runtime that offloads graphics tasks and minimizes interference, (2) cross-OS buffer projection that shares a rendering buffer with the Android host to eliminate redundant cross-OS copies, and (3) a PMU-guided predictor for real-time resource adjustment. Across the tested workload combinations, these mechanisms reduce the arithmetic-mean interference ratio by 31.83%, with a virtualization-overhead premium of 9.19 percentage points over a GPU-passthrough baseline. CarDroid was piloted and validated on production cockpit platforms across 10 vehicle models at 9 automotive companies.
- Open Access
- 4 September 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 23 (4) , 1-26
UVirtio: Enabling Ubiquitous Resource Sharing for RISC-V Industrial Edge Devices
The proliferation of IoT devices necessitates ubiquitous operating systems (UOS) for dynamic industrial edge scenarios, which face challenges including real-time demands and resource fragmentation. Existing virtualization methods are often too heavy or inflexible for these environments. In this article, we present UVirtio, a lightweight ubiquitous virtualization mechanism that enables efficient resource sharing across distributed edge devices. UVirtio introduces a device-profile-based virtual hardware abstraction layer that minimizes performance overhead. The system facilitates the collaboration and aggregation of edge devices, improving the throughput of sensor data by over 37.6% and enabling complex tasks such as face recognition on pooled AI accelerators. Furthermore, UVirtio implements a live migration mechanism using differential packing, achieving sub-40 millisecond downtime for dynamic resource reallocation, thus providing a scalable and agile virtualization solution for the ubiquitous computing frontier. Our work is open source at https://github.com/muliangshou/UVirtio/tree/main .
- 4 September 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 23 (4) , 1-26
Open AccessUVirtio: Enabling Ubiquitous Resource Sharing for RISC-V Industrial Edge Devices
The proliferation of IoT devices necessitates ubiquitous operating systems (UOS) for dynamic industrial edge scenarios, which face challenges including real-time demands and resource fragmentation. Existing virtualization methods are often too heavy or inflexible for these environments. In this article, we present UVirtio, a lightweight ubiquitous virtualization mechanism that enables efficient resource sharing across distributed edge devices. UVirtio introduces a device-profile-based virtual hardware abstraction layer that minimizes performance overhead. The system facilitates the collaboration and aggregation of edge devices, improving the throughput of sensor data by over 37.6% and enabling complex tasks such as face recognition on pooled AI accelerators. Furthermore, UVirtio implements a live migration mechanism using differential packing, achieving sub-40 millisecond downtime for dynamic resource reallocation, thus providing a scalable and agile virtualization solution for the ubiquitous computing frontier. Our work is open source at https://github.com/muliangshou/UVirtio/tree/main .