Mathieu Moreau

Raman thermometry is a powerful technique for sub-microscale thermal measurements on semiconductor-based devices, provided that the active region remains accessible and is not obscured by metallization. Since pure metals do not exhibit Raman scattering, traditional Raman thermometry becomes ineffective in such cases. To overcome this limitation, we propose the use of atomically thin Two-Dimensional materials as local temperature sensors. These materials generate Raman spectra at the nanoscale, enabling highly precise absolute surface temperature measurements. In this study, we investigate the feasibility and effectiveness of this approach by applying it to power devices, including a calibrated gold resistor and an SiC Junction Barrier Schottky (JBS) diode. We assess the processing challenges and measurement reliability of 2D materials for thermal characterization. To validate our findings, we complement Raman thermometry with thermoreflectance measurements, which are well suited for metallized surfaces. For example, on the serpentine resistor, Raman thermometry applied to the 2D material yielded a thermal resistance of 22.099 °C/W, while thermoreflectance on the metallic surface measured 21.898 °C/W. This close agreement suggests good thermal conductance at the metal/2D material interface. The results demonstrate the potential of integrating 2D materials as effective nanoscale temperature probes, offering new insights into thermal management strategies for advanced electronic components. Additionally, thermal simulations are conducted to further analyze the thermal response of these devices under operational conditions. Furthermore, we investigate two 2D material integration methods, transfer and direct growth, and evaluate them through measured thermal resistances for the SiC JBS diode, highlighting the influence of the deposition technique on thermal performance.

One of the important features of Resistive RAM (RRAM) is its conductance modulation, which makes it suitable for neuromorphic computing systems. In this paper, the conductance modulation of Oxide-based RAM (OxRAM) devices is evaluated based on experimental data to reveal its inherent analog synaptic behavior. A test chip made of a classical 1T-1R elementary memory array is used to demonstrate the conductance modulation. Using an array of cells, as opposed to an isolated cell, allows to catch temporal as well as spatial variabilities. Thus, the multiple resistance levels capability of OxRAMs is assessed in a more realistic context. Two different programming techniques are used to program the OxRAM cells. The first approach leverages on RESET (RST) voltage control. The second approach relies on compliance current control during the SET operation. In both approaches, although multiple resistance levels can be easily obtained, it is demonstrated that a successful implementation of a reliable conductance modulation scheme mainly depends on the ability to precisely control the impact of variability on the different conductance levels obtained after the programming operation.

Characterizing and quantifying the endurance of Resistive RAM devices is critical to assess their reliability for integration in electronic systems. This paper proposes a novel characterization methodology for rapid detection of RRAMs reliability issues during endurance tests. A test structure consisting of an array of non-addressable RRAM memory cells with parallel connection of all the memory elements is used for this purpose. The test structure fills the gap between isolated cells and circuit level endurance tests as it combines the test speed of an isolated cell while providing at the same time data from multiple devices. Endurance tests are conducted while monitoring RRAM electrical parameters of interest for each switching cycle. Experimental results show that most studies that claimed high endurance without capturing all switching cycles, or by considering an isolated cell, lead to an overestimation of the endurance. Finally, an endurance failures mitigation scheme based on RRAM current sensing in the RESET direction is presented to improve the endurance.

RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell (MLC) RRAM operation without the need of any read verification. RRAM quad-level cell (QLC) capability with 4 bits/cell is demonstrated for the first time. QLC is implemented based on a strict control of the cell programming current of 1T-1R HfO₂-based RRAM cells. From a design standpoint, a self-adaptive write termination circuit is proposed to control the RESET operation and provide an accurate tuning of the analog resistance value of each cell of a memory array. The different resistance levels are obtained by varying the compliance current in the RESET direction. Impact of variability on resistance margins is simulated and analyzed quantitatively at the circuit level to guarantee the robustness of the proposed MLC scheme. The minimal resistance margin reported between two consecutive states is 2.1 kΩ along with an average energy consumption and latency of 25 pJ/cell and 1.65 μs, respectively.

Energy efficiency remains one of the main factors for improving the key performance markers of RRAMs to support IoT edge devices. This paper proposes a simple and feasible low power design scheme which can be used as a powerful tool for energy reduction in RRAM circuits. The design scheme is exclusively based on current control during write and read operations and ensures that write operations are completed without wasted energy. Self-adaptive write termination circuits are proposed to control the RRAM current during FORMING, RESET and SET operations. The termination circuits sense the programming current and stop the write pulse as soon as a preferred programming current is reached. Simulation results demonstrate that an appropriate choice of the programming currents can help obtain 4.1X improvement in FORMING, 9.1X improvement in SET and 1.12X improvement in RESET energy. Also, the possibility to have a tight control over the RESET resistance is demonstrated. READ energy optimization is also covered by leveraging on a differential sense amplifier offering a programmable current reference. Finally, an optimal trade-off between energy consumption during SET/RESET operations and an acceptable read margin is established according to the final application requirements.

Static Random-Access Memories (SRAMs) are an integral part of the chip industry, occupying a noticeable share of the memory market due to their high performance and compatibility with CMOS technology. Traditional SRAMs lack the capability to retain data after power-off, restricting their availability in applications such as battery-powered mobile devices where non-volatility associated with zero-leakage currents is needed. This paper presents a novel Non-Volatile SRAMs (NVSRAMs) device based on Resistive RAM (RRAM) technology. A comparison between SRAM and NVSRAM performances is proposed at both cell and memory array level. The comparison covers several metrics such as power consumption, area and design complexity. The presented circuits are implemented in a 130-nm high voltage CMOS technology from STMicroelectronics.

A novel True Random Number Generator circuit fabricated in a 130 nm HfO ₂ -based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, all the cells of the memory array are addressed at the same time while the current provided to the circuit is limited to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, other cells are slightly programmed to reach an intermediate resistance state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed twelve NIST tests out of fifteen. Compared to state-of-the-art resistive RAM-based true random number generators, our proposed methodology is the first one to leverage on programming current limitation at a memory array level.

A novel True Random Number Generator circuit fabricated in a 130nm HfO ₂ -based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, the voltage applied to the cells of the memory array is fixed at the median SET voltage of the distribution, to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed eleven NIST tests out of fifteen without any post-processing.