Xiaoyang Wang
Xiaoyang Wang has a total of 38 co-authors. Here are the top co-authors by number of shared publications:
- Guangyu Sun
Peking University, Beijing, Beijing, CHINA
2 shared publications - Jiwu Shu
Tsinghua University, Beijing, China
2 shared publications Chao Yao
Peking Univ, Sch Elect Engn & Comp Sci, Beijing, Peoples R China
1 shared publication- Cong Wang
Renaissance Computing Institute
1 shared publication - Dongdong Hao
Xiamen University, Xiamen, China
1 shared publication Guangyu Sun
Peking Univ, CECA, Beijing, Peoples R China
1 shared publication
Latest Publications
- Open Access
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 1593-1607
Breaking Host-Wide Blocking: Boundary-Closure SCSI Error Handling
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 1593-1607
Open AccessBreaking Host-Wide Blocking: Boundary-Closure SCSI Error Handling
- Open Access
- 22 June 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-8
A 28nm RAID-on-Chip SoC Using On-Chip SRAM and Xfer-Driven Transfers
- 22 June 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-8
Open AccessA 28nm RAID-on-Chip SoC Using On-Chip SRAM and Xfer-Driven Transfers
- Open Access
- 20 December 2023
- Published by EWA Publishing in Theoretical and Natural Science
- Vol. 27 (1) , 180-184
Role of digital epidemiological technologies in controlling COVID-19: Cases review
The pandemic of COVID-19 had not only been testing the existing health care system globally, but also highlighting the need for more innovative and adaptive methods in dealing with new health threats. Digital technology become one of the most effective and efficient strategies in terms of controlling and monitoring the outbreak of this disease. These digital strategies will serve a significant role in providing valuable insights in disease and virus control for any upcoming event. This paper aims to discuss and evaluate the roles of digital technology methods in addressing COVID-19 pandemic, while focusing primarily on two case studies: COVIDSafe App from Australia and the EU’s Digital COVID Certificate. While confronting the challenge raised by COVID-19, the world had invented critical digital tools as instruments to monitor, track, and manage the spread of virus. By taking a deeper look at the history, technology, and application of the successful cases, the author hopes to draw important lessons from these experiences, and foreshadowing some broader potentials for their future development and usage. Additionally, the author also analyzes the legal and privacy concerns that may come with the adaption of digital technology in fighting the pandemic, and underscore the implication of technological methods advancement for future health crisis.
- 20 December 2023
- Published by EWA Publishing in Theoretical and Natural Science
- Vol. 27 (1) , 180-184
Open AccessRole of digital epidemiological technologies in controlling COVID-19: Cases review
The pandemic of COVID-19 had not only been testing the existing health care system globally, but also highlighting the need for more innovative and adaptive methods in dealing with new health threats. Digital technology become one of the most effective and efficient strategies in terms of controlling and monitoring the outbreak of this disease. These digital strategies will serve a significant role in providing valuable insights in disease and virus control for any upcoming event. This paper aims to discuss and evaluate the roles of digital technology methods in addressing COVID-19 pandemic, while focusing primarily on two case studies: COVIDSafe App from Australia and the EU’s Digital COVID Certificate. While confronting the challenge raised by COVID-19, the world had invented critical digital tools as instruments to monitor, track, and manage the spread of virus. By taking a deeper look at the history, technology, and application of the successful cases, the author hopes to draw important lessons from these experiences, and foreshadowing some broader potentials for their future development and usage. Additionally, the author also analyzes the legal and privacy concerns that may come with the adaption of digital technology in fighting the pandemic, and underscore the implication of technological methods advancement for future health crisis.
- Open Access
- 9 November 2023
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Embedded Computing Systems
- Vol. 22 (6) , 1-30
FD-CNN: A Frequency-Domain FPGA Acceleration Scheme for CNN-Based Image-Processing Applications
In the emerging edge-computing scenarios, FPGAs have been widely adopted to accelerate convolutional neural network (CNN)–based image-processing applications, such as image classification, object detection, and image segmentation, and so on. A standard image-processing pipeline first decodes the collected compressed images from Internet of Things (IoTs) to RGB data, then feeds them into CNN engines to compute the results. Previous works mainly focus on optimizing the CNN inference parts. However, we notice that on the popular ZYNQ FPGA platforms, image decoding can also become the bottleneck due to the poor performance of embedded ARM CPUs. Even with a hardware accelerator, the decoding operations still incur considerable latency. Moreover, conventional RGB-based CNNs have too few input channels at the first layer, which can hardly utilize the high parallelism of CNN engines and greatly slows down the network inference. To overcome these problems, in this article, we propose FD-CNN, a novel CNN accelerator leveraging the partial-decoding technique to accelerate CNNs directly in the frequency domain. Specifically, we omit the most time-consuming IDCT (Inverse Discrete Cosine Transform) operations of image decoding and directly feed the DCT coefficients (i.e., the frequency data) into CNNs. By this means, the image decoder can be greatly simplified. Moreover, compared to the RGB data, frequency data has a narrower input resolution but has 64× more channels. Such an input shape is more hardware friendly than RGB data and can substantially reduce the CNN inference time. We then systematically discuss the algorithm, architecture, and command set design of FD-CNN. To deal with the irregularity of different CNN applications, we propose an image-decoding-aware design-space exploration (DSE) workflow to optimize the pipeline. We further propose an early stopping strategy to tackle the time-consuming progressive JPEG decoding. Comprehensive experiments demonstrate that FD-CNN achieves, on average, 3.24×, 4.29× throughput improvement, 2.55×, 2.54× energy reduction and 2.38×, 2.58× lower latency on ZC-706 and ZCU-102 platforms, respectively, compared to the baseline image-processing pipelines.
- 9 November 2023
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Embedded Computing Systems
- Vol. 22 (6) , 1-30
Open AccessFD-CNN: A Frequency-Domain FPGA Acceleration Scheme for CNN-Based Image-Processing Applications
In the emerging edge-computing scenarios, FPGAs have been widely adopted to accelerate convolutional neural network (CNN)–based image-processing applications, such as image classification, object detection, and image segmentation, and so on. A standard image-processing pipeline first decodes the collected compressed images from Internet of Things (IoTs) to RGB data, then feeds them into CNN engines to compute the results. Previous works mainly focus on optimizing the CNN inference parts. However, we notice that on the popular ZYNQ FPGA platforms, image decoding can also become the bottleneck due to the poor performance of embedded ARM CPUs. Even with a hardware accelerator, the decoding operations still incur considerable latency. Moreover, conventional RGB-based CNNs have too few input channels at the first layer, which can hardly utilize the high parallelism of CNN engines and greatly slows down the network inference. To overcome these problems, in this article, we propose FD-CNN, a novel CNN accelerator leveraging the partial-decoding technique to accelerate CNNs directly in the frequency domain. Specifically, we omit the most time-consuming IDCT (Inverse Discrete Cosine Transform) operations of image decoding and directly feed the DCT coefficients (i.e., the frequency data) into CNNs. By this means, the image decoder can be greatly simplified. Moreover, compared to the RGB data, frequency data has a narrower input resolution but has 64× more channels. Such an input shape is more hardware friendly than RGB data and can substantially reduce the CNN inference time. We then systematically discuss the algorithm, architecture, and command set design of FD-CNN. To deal with the irregularity of different CNN applications, we propose an image-decoding-aware design-space exploration (DSE) workflow to optimize the pipeline. We further propose an early stopping strategy to tackle the time-consuming progressive JPEG decoding. Comprehensive experiments demonstrate that FD-CNN achieves, on average, 3.24×, 4.29× throughput improvement, 2.55×, 2.54× energy reduction and 2.38×, 2.58× lower latency on ZC-706 and ZCU-102 platforms, respectively, compared to the baseline image-processing pipelines.
- 27 March 2020
- Published by Springer Nature in Journal of Computer Science and Technology
- Vol. 35 (2) , 453-467
Bigflow: A General Optimization Layer for Distributed Computing Frameworks
- 27 March 2020
- Published by Springer Nature in Journal of Computer Science and Technology
- Vol. 35 (2) , 453-467
Bigflow: A General Optimization Layer for Distributed Computing Frameworks
- 24 September 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Network
- Vol. 33 (2) , 166-173
EdgeFlow: Open-Source Multi-layer Data Flow Processing in Edge Computing for 5G and Beyond
Edge computing has evolved to be a promising avenue to enhance system computing capability by offloading processing tasks from the cloud to edge devices. In this article, we propose a multi-layer edge computing framework called EdgeFlow. In this framework, different nodes ranging from edge devices to cloud data centers are categorized into corresponding layers and cooperate for data processing. EdgeFlow can deal with the trade-off between the computing and communication capabilities so that the tasks can be assigned to each layer optimally. At the same time, resources are carefully allocated throughout the whole network to mitigate performance fluctuation. The proposed open-source data flow processing framework is implemented on a platform that can emulate various computing nodes in multiple layers and corresponding network connections. Evaluated on the face recognition scenario, EdgeFlow can significantly reduce task finish time and perform more tolerance to run-time variations, compared with pure cloud computing, pure edge computing, and Cloudlet. Potential applications of EdgeFlow, including network function virtualization, Internet of Things, and vehicular networks, are also discussed at the end of this article.
- 24 September 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Network
- Vol. 33 (2) , 166-173
EdgeFlow: Open-Source Multi-layer Data Flow Processing in Edge Computing for 5G and Beyond
Edge computing has evolved to be a promising avenue to enhance system computing capability by offloading processing tasks from the cloud to edge devices. In this article, we propose a multi-layer edge computing framework called EdgeFlow. In this framework, different nodes ranging from edge devices to cloud data centers are categorized into corresponding layers and cooperate for data processing. EdgeFlow can deal with the trade-off between the computing and communication capabilities so that the tasks can be assigned to each layer optimally. At the same time, resources are carefully allocated throughout the whole network to mitigate performance fluctuation. The proposed open-source data flow processing framework is implemented on a platform that can emulate various computing nodes in multiple layers and corresponding network connections. Evaluated on the face recognition scenario, EdgeFlow can significantly reduce task finish time and perform more tolerance to run-time variations, compared with pure cloud computing, pure edge computing, and Cloudlet. Potential applications of EdgeFlow, including network function virtualization, Internet of Things, and vehicular networks, are also discussed at the end of this article.
- 3 September 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 68 (2) , 239-254
RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses
Although emerging non-volatile memories (NVMs) have been comprehensively studied to design next-generation memory systems, the symmetry of the crossbar structure adopted by most NVMs, such as PCM, RRAM and 3D XPoint, has not been addressed. In this work, we argue that crossbar-based NVMs can enable dual-addressing memory architecture, i.e. RC-NVM, to support both row- and column-oriented memory accesses for workloads with different access patterns. Through circuit-level analysis, we first prove that such a dual-addressing architecture is only practical with crossbar-based NVMs rather than DRAM. Then, we introduce the RC-NVM architecture from bank, chip and module levels, and propose RC-NVM aware memory controller. We also address the challenges to implement the end-to-end RC-NVM system. Especially, we design a novel protocol to solve the cache synonym problem with very little overhead. Finally, we introduce the deployment of RC-NVM for in-memory databases (IMDBs) and evaluate its performance with IMDBs and well-optimized general matrix multiply (GEMM) workloads. Experimental results show that with only 10% area overhead 1) the memory access performance of IMDBs can be improved up to 14.5X, and 2) for GEMM, RC-NVM naturally supports SIMD operations and outperforms the best tiled layout by 19%.
- 3 September 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 68 (2) , 239-254
RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses
Although emerging non-volatile memories (NVMs) have been comprehensively studied to design next-generation memory systems, the symmetry of the crossbar structure adopted by most NVMs, such as PCM, RRAM and 3D XPoint, has not been addressed. In this work, we argue that crossbar-based NVMs can enable dual-addressing memory architecture, i.e. RC-NVM, to support both row- and column-oriented memory accesses for workloads with different access patterns. Through circuit-level analysis, we first prove that such a dual-addressing architecture is only practical with crossbar-based NVMs rather than DRAM. Then, we introduce the RC-NVM architecture from bank, chip and module levels, and propose RC-NVM aware memory controller. We also address the challenges to implement the end-to-end RC-NVM system. Especially, we design a novel protocol to solve the cache synonym problem with very little overhead. Finally, we introduce the deployment of RC-NVM for in-memory databases (IMDBs) and evaluate its performance with IMDBs and well-optimized general matrix multiply (GEMM) workloads. Experimental results show that with only 10% area overhead 1) the memory access performance of IMDBs can be improved up to 14.5X, and 2) for GEMM, RC-NVM naturally supports SIMD operations and outperforms the best tiled layout by 19%.