Lionel Trojman

This work introduces a novel 128-bit transient effect ring oscillator (TERO)-based physically unclonable function (PUF) designed for Intel MAX 10 field-programmable gate arrays (FPGAs). A reliable PUF solution suitable for security applications targeting high stability and area efficiency is presented. The proposed cell consists of two cross-coupled reconfigurable ring oscillators (ROs) aiming to achieve zero-observed instability at both golden key (GK) and under temperature variations. Conversely to the conventional application-specific integrated circuits (ASIC) approaches, which use the mean cycles to collapse (CTC), here the calibration process was performed by considering the CTC standard deviation extracted at GK conditions, namely, 1.2 V and $25~^{\circ }$ C. The experimental results demonstrate that after the calibration process and considering a 1.64% of masked bits, the proposed solution shows a bit error rate (BER) lower than $\mathbf {1.56\times 10^{-4}\%}$ , the minimum observable quantity for the adopted statistical set across the entire analyzed temperature range. Further, the solution also shows an excellent uniqueness of 49.78%, close to the ideal value of 50%. This is achieved at the cost of two logic array blocks (LABs) per bit.

Despite the high performance of the existing embedding approaches for Aspect-Based Sentiment Analysis (ABSA), such as Word2Vec and GloVe, they still have several limitations, mainly in contextual understanding and relational insights of natural language, especially in complex and long sentences. This paper presents a novel approach that enhances ABSA by integrating knowledge graphs into a transformer model, where the graphs are automatically built from raw text without requiring external resources, making the system adaptable and fully data-driven. Our approach allows a better understanding of context and relationships between entities, by combining of the contextual understanding of BERT with the relational insights provided by Node2Vec, a graph-based embedding technique. In this paper, we benchmark our hybrid embedding technique with the existing state-of-the-art embedding techniques. Specifically, we compare traditional embeddings, such as Word2Vec and GloVe, against BERT for textual input, while also exploring Word2Vec and Node2Vec for graph-based embeddings. Our experiments demonstrate that combining BERT’s deep contextual embeddings with the structural insights of Node2Vec leads to promising improvements in sentiment classification performance. Our model achieved 98% accuracy on SemEval2015 Restaurant dataset. These results demonstrate that integrating both contextual and relational information significantly enhances the performance of ABSA models, thereby making them more effective at capturing nuanced sentiment relationships. The proposed model’s modular design also allows flexible integration of alternative embeddings or graph configurations, making it suitable for broader sentiment analysis applications beyond the benchmark datasets.

Sentiment analysis involves using computational methods to identify and classify opinions expressed in text, with the goal of determining whether the writer's stance towards a particular topic, product, or idea is positive, negative, or neutral. However, sentiment analysis in Arabic presents unique challenges due to the complexity of Arabic morphology and the variety of dialects, which make language classification even more difficult. To address these challenges, we conducted to investigation and overview the techniques used in the last five years for embedding and classification of Arabic sentiment analysis (ASA). We collected data from 100 publications, resulting in a representative dataset of 2,300 detailed records that included attributes related to the dataset, feature extraction, approach, parameters, and performance measures. Our study aimed to identify the most powerful approaches and best model settings by analyzing the collected data to identify the significant parameters influencing performance. The results showed that Deep Learning and Machine Learning were the most commonly used techniques, followed by lexicon and transformer-based techniques. However, Deep Learning models were found to be more accurate for sentiment classification than other Machine Learning models. Furthermore, multi-level embedding was found to be a significant step in improving model accuracy.

This paper introduces SIMPLY+, an advanced Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM)-based Logic-in-Memory (LIM) architecture that evolves from the previously proposed smart material implication (SIMPLY) logic scheme. More specifically, the latter is enhanced by incorporating additional circuitry to enhance the reliability of preliminary read operations. In this study, the proposed architecture is benchmarked against its conventional counterpart. Obtained results show a significant improvement in terms of reliability, i.e., the nominal read margin (RM) by a factor of ~3-4× and accordingly the bit error rate (BER) by more than four orders of magnitude. These improvements come at minimal cost in terms of circuit area and complexity compared to the conventional SIMPLY design. Overall, this research establishes SIMPLY+ as a promising solution for the design of reliable and energy-efficient in-memory computing architectures.

En 2016, nous avons lancé le premier master de Nanoélectronique en Équateur à l’Universidad San Francisco de Quito (USFQ). Il s’agit d’un master en Double Diplôme dont le Master 1 (M1) se fait en Equateur et le Master 2 (M2) soit en France (Institut National Polytechnique de Toulouse, INPT) soit en Italie (Université de Calabres, UNICAL). Parmi les cours proposés le cours de design de microprocesseur de 48h est divisé en 2 parties dont une se concentrant sur le design d’un VSM (Very Simple Microprocessor). Dans une pédagogie de type classe inversée, une approche de type Apprentissage Par Projet (APP) a été choisie en utilisant comme support l’outil de design Microwind, logiciel de design de circuits intégrés incluant une perspective technologique. Ce type de travail a été reproduit tous les ans et Microwind a continué à intégrer de nouveaux noeuds technologiques avec de nouvelle architectures : planar, FinFET et plus récemment Nano-Sheet FET. De cette façon chaque nouvelle promotion peut apprendre à pratiquer l’intégration des VSM « customized » avec la possibilité d’intégrer des noeuds technologiques les plus avancés.

Este trabajo tiene como objetivo estudiar la degradación de los diodos de barrera Schottky (SBD) con una terminación de borde cerrado (GET) bajo condiciones de estrés en estado de encendido en tecnologías de 200V y 650V. Después de todos los experimentos de estrés, se observa un comportamiento recuperable, que indica el atrapamiento de cargas en defectos preexistentes y no creación de nuevas trampas. Un análisis estadístico amplio demuestra una mayor confiabilidad y una vida útil más larga en comparación con trabajos anteriores en una tecnología de 200 V. Para la tecnología de 650V, se analizaron variaciones en el ánodo como una doble capa GET y el uso de Al₂O₃/SiO₂ como dieléctrico. Se obtuvo una menor degradación total en el segundo caso gracias a la compensación entre los mecanismos de resistencia de encendido (R_ON) y voltaje de encendido (V_TON). Se observan algunas diferencias sistemáticas en la degradación de los parámetros según la ubicación de la oblea, probablemente causadas por variaciones relacionadas con el proceso. Mediante el uso de la técnica de pares coincidentes (MP), se ha demostrado que se pueden obtener distribuciones de probabilidad caracterizadas por pendientes de Weibull únicas sobre la oblea que podrían permitir una mejor caracterización de la confiabilidad intrínseca de estos dispositivos.

In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the 32 nm technology, while lookup tables (LUT) resulting from a physics model have been applied for the TFET. To consider the parasitic effects for the circuit performances, the 32 nm-based circuits have been laid out, while a parasitic model has been included in the TFET LUT for circuit implementation. In this work, the post-layout simulations, including parasitic, demonstrate for conventional CCDD circuits that TFET technology has a larger dynamic range (DR) (>60%) and better 1 V-sensitivity than the 32 nm planar technology has. Note that, in this case, the figure of merit defined by the Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE) remains somewhat similar. On the other hand, topology proposing better VCE at the cost of low PCE shows lower performance than expected in 32 nm than in reported data for larger technology nodes (e.g., 180 nm). The TFET-based circuit shows a PCE of 70%, VCE of 82% with an 8 dB DR (>60%), and the best 1 V-sensitivity in this work. Because of the low-bias condition and the good reverse current blocking (unidirectional channel), the TFET offers new perspectives for RF-DC rectifier/multiplier topology, which are usually limited with planar technology.

The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin are compared with 10 nm FinFETs for a wide voltage supply ranging from 200 to 600 mV with a specific focus on the ultra-low voltage domain. A calibration process is carried out to ensure the same off-current and extrinsic capacitance in both devices. The TFETs presented a high advantage in terms of delay as well as a penalty in energy consumed. As a result, the TFET circuits show a better Energy-Delay trade-off in voltages as low as 350 m V. This is explained by a larger capacitance caused by the nature of the intrinsic materials chosen of the device modelling.