Vincent Riess

This research work presents the fabrication and characterization of ultra-thin fully integrated transmitter circuits. By moving bendable technology into the 190-GHz band, it is possible to implement complete transmitter systems or sensor nodes, including on-chip antennas, on a single chip without the need for surrounding circuits, thus increasing system performance and reducing cost. To fabricate such thin chips, a standard 700- $\mathrm {\mu }\text{m}$ fully processed SiGe BiCMOS wafer was thinned to a thickness of only 20 $\mathrm {\mu }\text{m}$ making the silicon bendable. The transmitter, which consists of a voltage-controlled oscillator, a power amplifier, and an on-chip antenna, was characterized by comparing thinned and standard thickness samples. Therefore, a maximum relative deviation of the oscillator frequency tuning of less than 2% was found. The oscillation frequency of the chip is measured in a bent state, resulting in a maximum relative deviation for bend radii of up to 4 mm of only 1%. Considering a maximum output power deviation of 4.6 dB, the presented approach proves to be feasible for the design of flexible high-performance integrated systems. This enables novel applications in the field of medicine, wearable electronics, and the Internet of Things.

This work presents a direct-conversion receiver for G-band applications formed by a cascaded single-stage distributed amplifier optimized for low noise, a single-balanced active mixer with inductive peaking and broadband RF matching, and a local oscillator (LO) driver. The receiver is optimized for reduced DC and LO power consumption, while practical levels of linearity and noise are retained. The complete receiver and of the stand-alone mixer are implemented in 0.62 mm ² and 0.39 mm ² of a 130 nm SiGe BiCMOS technology with 450 GHz maximum-oscillation frequency. The measured receiver saturated gain in LO compression is 17 dB with a 6 dB band of 60 GHz and a 3 dB band of 30 GHz, while the input power which compresses the gain by 1 dB ( P _in1dB ) is -35 dBm. The simulated receiver double-sideband noise figure is 11 dB. Finally, the circuit requires an LO power of -17 dBm at 170 GHz and a DC power of 98 mW. The measured gain of the mixer is -13 dB with a 3 dB band of 70 GHz. The component P _in1dB is -20 dBm for -18 dBm LO power and 53 mW DC power. These circuits offer one of the largest operation bandwidth together with one of the lowest DC and LO power consumption against the state of the art.

A frequency quadrupler for the up-conversion of a 63.75-GHz signal to an output frequency of 255 and 12.7 GHz of bandwidth for use in a local oscillator chain is presented. The presented circuit extends the common push-push architecture to a single-stage frequency quadrupler and improves upon existing designs concerning frequency of operation and conversion core efficiency. By replacing the usual 2x2 architectures with the presented solution, the total dc power consumption can be reduced by over 75% with respect to state-of-the-art designs, while maintaining useful output power levels. To showcase the performance of the core, the design abstains from any buffers at the input or output. Consuming 22.4 mW the circuit produces -8.4 dBm of output power. Excluding the losses in the passive input network, the circuit achieves a conversion loss of 4.4 dB. The fundamental suppression is higher than 40 dB.

In this paper, a quadrature down-conversion mixer for low-power wireless communication systems at 180 GHz is presented. A broadband six-port junction is combined with four power detectors for power-efficient demodulation of the inphase and quadrature differential baseband signals. Two differential amplifiers are integrated at the baseband outputs, which are dominating the total dc power consumption of 141 mW. With -9.3 dBm of power from a local oscillator, a maximum conversion gain of 13 dB is demonstrated in a -3 dB RF band from 156 GHz to 195 GHz, resulting in a symmetric bandwidth of 15 GHz in the baseband.

A frequency multiplier for the direct generation of the fourth, sixth, or eighth harmonic of an input signal in a single stage is presented. By analyzing the effect of clipping both half-waves in the output signal asymmetrically, beneficial clipping thresholds are identified. Based on the ideal signal analysis, circuit simulations are carried out to investigate and implement the proposed approach using a heterojunction bipolar transistor (HBT) push-push cascode amplifier, which enables the independent adjustment of the clipping thresholds. Finally, the circuit is combined with an input balun and an output amplifier and fabricated in a 130-nm SiGe BiCMOS process for verification. Measurement results of the prototype are compared with simulations based on available VBIC and HICUM models for the HBTs, providing insight on their capabilities to predict the high-order nonlinear effects essential for the operation of the presented multiplier. The circuit performs in general agreement with the HICUM model simulations and represents a versatile times-four, times-six, and times-eight frequency multiplier with a 37-GHz output-referred bandwidth from 173 to 210 GHz and an output power of up to -6 dBm. To the the best of the authors' knowledge, the conversion gain of 10 dB is the highest in class reported up to date, even when compared to III/V-based circuits. A maximum harmonic suppression of 40 dB and a total dc power consumption of 63 mW are measured.

This work presents an amplifier for mm-wave applications reaching a peak gain of 26 dB with a usable bandwidth of up to 98 GHz. The design is optimized for an operating frequency between 100 GHz to 200 GHz and can deliver medium output power levels up to 3 dBm. The total dc power consumption is 70mW. To allow the use in ultra wideband communication systems the group delay variation is kept below 5 ps. As additional feature a power detector with a large dynamic range, covering the linear region of the amplifier, is integrated at the output to allow a direct measurement of the outgoing signal levels. The circuit is fabricated in a 130 nm SiGe BiCMOS process with fmax of 500 GHz and covers a core area of only 0.15 mm ² .

This paper presents a fully-differential frequency doubler integrated in 130 nm SiGe BiCMOS technology. To obtain a differential output signal, the conventional push-push topology is extended. The benefits of this approach are investigated with non-linear circuit analysis and discussed. While both the conventional push-push doubler and the Gilbert-cell doubler only suppress the odd harmonics, the extended topology enables the further suppression of the fourth harmonic. The circuit requires a set of phase-shifted versions of the input signal, which are generated on-chip with a polyphase filter. The proposed approach is validated with measurements of the fabricated circuit: an output power of -4 dBm at the 1 dB compression point with a -3 dB output bandwidth of 10 GHz from 55.6 GHz to 65.6 GHz is reported. With a low power consumption of 23.5 mW, a conversion gain of -15 dB and a fundamental suppression of 42 dB are achieved around the center frequency. A method to improve the conversion gain is discussed in the conclusion.