Xiaoyan Li

The three-level inverter with reduced active switch count (RASC) has been proposed to realize multilevel output waveform with reduced system cost. The existing modulation strategy results in high switching losses of power switches, which cannot realize the efficient operation of the inverter system. This article further proposes a simultaneous switching loss reduction and neutral-point voltage (NPV) balance control scheme for the RASC three-level inverter. At first, the selection of basic vectors is conducted in different regions of the space vector diagram (SVD). The clamping modes that have opposite effects on the NPV are analyzed, based on which four types of switching sequences are designed. A hysteresis control approach is introduced to select the appropriate sequence, so as to balance the NPV and guarantee the reliable operation of the system. The feasibility and effectiveness of the proposed method are verified via simulated and hardware-based experimental results.

Three-level grid-tied converters (GTCs) with modified LCL (MLCL) filters are widely used in photovoltaic generation due to their effectiveness in attenuating leakage currents. However, MLCL filters also introduce a significant common-mode (CM) resonant current (CMRC), which poses a risk to system stability. Furthermore, the discontinuous pulse width modulation (DPWM) technique, originally developed to improve converter efficiency, is incompatible with MLCL filters and exacerbates the CMRC. Consequently, a conflict arises between CMRC suppression and efficiency enhancement. In this article, we propose a filter-based DPWM strategy and a robust CM-loop controller to address this problem. Specifically, the filter-based DPWM effectively reduces CMRC excitation sources while still ensuring a prolonged clamping time for each phase. The CM-loop controller, developed using loop-shaping theory, successfully suppresses CMRC and guarantees robust stability of the CM loop. The synergy between the filter-based DPWM strategy and the CM-loop controller simultaneously achieves CMRC suppression and efficiency enhancement. Experimental results demonstrate that the CMRC is reduced to below 300 mA, and the converter efficiency is improved by 2% under the light load condition and 0.5% under the heavy load condition.

The reduced switch count three-level inverter (RSC TLI) can reduce the number of power switches, but the conventional space vector modulation (SVM) method generates the large dc-link current ripple and reduces the dc-link capacitor reliability. This article proposes a novel dc-link current ripple reduction method, which is applicable to both balanced and unbalanced neutral-point (NP) voltage (NPV) conditions. Firstly, the duty cycles calculation of the conventional SVM method is introduced. To realize the dc-link current ripple reduction, the region division method is optimized by analyzing the range of the duty cycle distribution factor and combining the magnitude of output current. Doing so, the calculating complexity of duty cycles is reduced. Secondly, a deadbeat control method is designed for accurate and fast separate control of capacitor voltages. At last, appropriate switching sequences are arranged. Compared with the conventional SVM method, the dc-link current ripple of the proposed method is reduced by one-fourth and two-fifths in the high and low modulation indices, respectively, and maintains the rewarding quality of output currents with balanced and unbalanced NPVs. The feasibility and effectiveness of the proposed method are verified by simulations and experiments.

For three-level T-type inverter (3LT2I), the unbalanced neutral-point (NP) voltage is required in some photovoltaic (PV) generation systems. Meanwhile, the unbalanced NP voltage easily leads to the fault of power switches. However, the existing fault tolerant control (FTC) strategies are only capable of the balanced NP voltage conditions. In order to simultaneously realize the FTC and unbalanced NP voltage control (UNPVC), a half cycle FTC (HC-FTC) strategy and a whole cycle FTC (WC-FTC) strategy are proposed in this paper. The carrier is modified to avoid using the impossible switching states and realize FTC. Meanwhile, the mathematical models of NP current under both normal and fault conditions are established based on volt-second balance principle, and thereby the zero-sequence component (ZSC) derived by the model can be used to realize the UNPVC whether the switch is fault or not. In addition, the ZSC is selected in detail to improve the NP voltage control ability in HC-FTC. Furthermore, the application range of HC-FTC is obtained and the WC-FTC with wider application range is proposed. The two proposed strategies can be selected according to the requirements. Finally, experimental results validate the effectiveness of the proposed strategies.

The impedance-source (IS) three-level inverter has been put forward to implement buck-boost operation and obtain multi-level output waveforms. The virtual space vector modulation (VSVM) can balance the neutral-point voltage (NPV) in full power factors and modulation indices. This article further proposes a fast-processing implementation method of VSVM for IS three-level inverter. According to the relationship of three-phase modulation waves, a proper differential-mode voltage injection scheme is developed to control the NPV balance actively. In order to boost the dc input voltage, the maximum and minimum modulation waves are further moved upwards and downwards, and the shoot-through (ST) states are properly generated without affecting the normal ac output voltage. Doing so, the VSVM strategy for IS three-level inverter is simply implemented by carrier-based modulation (CBM) approach. The effectiveness of the proposed method is verified by experiments.

This article proposes a double phase shifted pulsewidth modulation (PWM) strategy to improve the quality of total output current in multiple parallel converters for the photovoltaic application with the advantage of being easy to implement/extend. Different from phase shifted PWM (PS-PWM), the additional modified angles are deduced and added in the initial phase shifted angles of carriers. The better total output current with lower total harmonic distortion can be achieved by modifying the phase shifted angles of carriers in each converter twice. The harmonic spectrum analysis shows that the proposed method could provide superior total output line voltage and total output current quality than conventional PS-PWM. The correctness and effectiveness of the proposed method are verified by the experiments in parallel three-phase two-level and three-level converters.

The T-type three-level inverter (T ² 3LI) topology has been extensively employed in various industrial applications. This article further proposes a novel series-connected T-type multi-level inverter (SCT ² MLI), whose phase leg is formed by two series-connected T-type three-level inverter phase legs. First, the basic operating principle of the SCT ² MLI is analyzed, and the impact mechanism of different switching states on the dc-link capacitor voltages is obtained. An improved selective harmonic elimination (ISHE) method is subsequently designed, which can simultaneously restrain the common-mode voltage (CMV) and eliminate the selective low -order harmonics, while the performance of ac output voltage is not influenced. In addition, the voltages across dc-side capacitor voltages are controlled by adopting redundant switching states. When using the proposed ISHE method, the CMV is significantly restricted in comparison with the traditional SHE method. The evaluation results prove the feasibility of the proposed method.

The series-parallel-type microgrid has been proposed to integrate various distributed generation (DG) units, such as photovoltaic (PV) and energy storage. This article further proposes a novel distributed and hierarchical control method for accurate power sharing and restoration of AC output voltage magnitude. First, the basic working principle of the series-parallel-type microgrid has been briefly introduced, based on which the proposed method is elaborated. Each converter module only communicates with its neighboring converter module, and the central controller is not needed, which avoids the failure of central controller on the whole system and increases the reliability. The correction values of AC voltage magnitude and angular frequency are calculated. The proposed method is suitable for both resistive-inductive (RL) and resistive-capacitive (RC) loads. Evaluation results are provided to validate the feasibility of the proposed method.

The LCCL filter can be employed with the transformerless inverter to mitigate the leakage current, which however generates the common-mode resonance current (CMRC) and oscillations in the inverter-side currents. Owing to the inherent features of the reduced switch count three-level inverter (RSC-TLI), the medium vectors are unable to be generated, which implies that the conventional method cannot be applied straightforward. This article presents a novel strategy to suppress the CMRC in the RSC-TLI with LCCL filter, which regulates the duty cycles of small vectors by using distribution factors. Compared to conventional passive damping technique, the CMRC and leakage current are restrained by the presented strategy. As a result, the oscillations of inverter-side currents are mitigated, while the system cost is reduced. Evaluation results confirm the feasibility of the presented method.