An-Jye Tzou

GaN HEMT has attracted a lot of attention in recent years owing to its wide applications from the high-frequency power amplifier to the high voltage devices used in power electronic systems. Development of GaN HEMT on Si-based substrate is currently the main focus of the industry to reduce the cost as well as to integrate GaN with Si-based components. However, the direct growth of GaN on Si has the challenge of high defect density that compromises the performance, reliability, and yield. Defects are typically nucleated at the GaN/Si heterointerface due to both lattice and thermal mismatches between GaN and Si. In this article, we will review the current status of GaN on Si in terms of epitaxy and device performances in high frequency and high-power applications. Recently, different substrate structures including silicon-on-insulator (SOI) and engineered poly-AlN (QST^®) are introduced to enhance the epitaxy quality by reducing the mismatches. We will discuss the development and potential benefit of these novel substrates. Moreover, SOI may provide a path to enable the integration of GaN with Si CMOS. Finally, the recent development of 3D hetero-integration technology to combine GaN technology and CMOS is also illustrated.

GaN has been widely used to develop devices for high-power and high-frequency applications owing to its higher breakdown voltage and high electron saturation velocity. The GaN HEMT radio frequency (RF) power amplifier is the first commercialized product which is fabricated using the conventional Au-based III–V device manufacturing process. In recent years, owing to the increased applications in power electronics, and expanded applications in RF and millimeter-wave (mmW) power amplifiers for 5G mobile communications, the development of high-volume production techniques derived from CMOS technology for GaN electronic devices has become highly demanded. In this article, we will review the history and principles of each unit process for conventional HEMT technology with Au-based metallization schemes, including epitaxy, ohmic contact, and Schottky metal gate technology. The evolution and status of CMOS-compatible Au-less process technology will then be described and discussed. In particular, novel process techniques such as regrown ohmic layers and metal–insulator–semiconductor (MIS) gates are illustrated. New enhancement-mode device technology based on the p-GaN gate is also reviewed. The vertical GaN device is a new direction of development for devices used in high-power applications, and we will also highlight the key features of such kind of device technology.

Most thin-film techniques require a multiple vacuum process, and cannot produce high-coverage continuous thin films with the thickness of a few nanometers on rough surfaces. We present a new ”paradigm shift” non-vacuum process to deposit high-quality, ultra-thin, single-crystal layers of coalesced sulfide nanoparticles (NPs) with controllable thickness down to a few nanometers, based on thermal decomposition. This provides high-coverage, homogeneous thickness, and large-area deposition over a rough surface, with little material loss or liquid chemical waste, and deposition rates of 10 nm/min. This technique can potentially replace conventional thin-film deposition methods, such as atomic layer deposition (ALD) and chemical bath deposition (CBD) as used by the Cu(In,Ga)Se₂ (CIGS) thin-film solar cell industry for decades. We demonstrate 32% improvement of CIGS thin-film solar cell efficiency in comparison to reference devices prepared by conventional CBD deposition method by depositing the ZnS NPs buffer layer using the new process. The new ZnS NPs layer allows reduction of an intrinsic ZnO layer, which can lead to severe shunt leakage in case of a CBD buffer layer. This leads to a 65% relative efficiency increase.

This paper reports the successful fabrication of a GaN-on-Si high electron mobility transistor (HEMT) with a 1702 V breakdown voltage (BV) and low current collapse. The strain and threading dislocation density were well-controlled by 100 pairs of AlN/GaN superlattice buffer layers. Relative to the carbon-doped GaN spacer layer, we grew the AlGaN back barrier layer at a high temperature, resulting in a low carbon-doping concentration. The high-bandgap AlGaN provided an effective barrier for blocking leakage from the channel to substrate, leading to a BV comparable to the ordinary carbon-doped GaN HEMTs. In addition, the AlGaN back barrier showed a low dispersion of transiently pulsed I_D under substrate bias, implying that the buffer traps were effectively suppressed. Therefore, we obtained a low-dynamic on-resistance with this AlGaN back barrier. These two approaches of high BV with low current collapse improved the device performance, yielding a device that is reliable in power device applications.

The flip chip ultraviolet light-emitting diodes (FC UV-LEDs) with a wavelength of 365 nm are developed with the ex situ reactive plasma deposited (RPD) AlN nucleation layer on patterned sapphire substrate (PSS) by an atmospheric pressure metal-organic chemical vapor deposition (AP MOCVD). The ex situ RPD AlN nucleation layer can significantly reduce dislocation density and thus improve the crystal quality of the GaN epitaxial layers. Utilizing high-resolution X-ray diffraction, the full width at half maximum of the rocking curve shows that the crystalline quality of the epitaxial layer with the (RPD) AlN nucleation layer is better than that with the low-temperature GaN (LT-GaN) nucleation layer. The threading dislocation density (TDD) is estimated by transmission electron microscopy (TEM), which shows the reduction from 6.8 × 10⁷ cm⁻² to 2.6 × 10⁷ cm⁻². Furthermore, the light output power (LOP) of the LEDs with the RPD AlN nucleation layer has been improved up to 30 % at a forward current of 350 mA compared to that of the LEDs grown on PSS with conventional LT-GaN nucleation layer.