Xu Bai
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Xu Bai has a total of 5 co-authors. Here are the top co-authors by number of shared publications:
Jianzhong Zhao
Smart Sensing R&D Centre, Institute of Microelectronics of Chinese Academy of Science, Beijing 100029, P. R. China
1 shared publication- Jianzhong Zhao
Smart Sensing R & D Centre, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
1 shared publication - Shi Zuo
Smart Sensing R & D Centre, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
1 shared publication Yumei Zhou
Smart Sensing R&D Centre, Institute of Microelectronics of Chinese Academy of Science, Beijing 100029, P. R. China
1 shared publication- Yumei Zhou
Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
1 shared publication
Latest Publications
- 4 April 2019
- Published by World Scientific Pub Co Pte Ltd in Journal of Circuits, Systems and Computers
- Vol. 29 (02)
A High Precision Output Impedance Calibration Technique for SST Transmitter
- 4 April 2019
- Published by World Scientific Pub Co Pte Ltd in Journal of Circuits, Systems and Computers
- Vol. 29 (02)
A High Precision Output Impedance Calibration Technique for SST Transmitter
- Open Access
- 22 March 2019
- Published by MDPI AG in Electronics
- Vol. 8 (3) , 350
A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology
This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 ps@2.5 Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.
- 22 March 2019
- Published by MDPI AG in Electronics
- Vol. 8 (3) , 350
Open AccessA 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology
This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 ps@2.5 Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.