Cristina Miccoli

We investigate the sustainable breakdown operation of lateral E-mode GaN high-electron mobility transistors. First, the dependence of the sustainable breakdown voltage (Vaval) on gate bias was investigated; a reduction in Vaval was observed at increased gate voltage, and ascribed to the progressively increasing sub-threshold conduction. Evidence for hole trapping under the gate was then obtained, by monitoring the threshold voltage variation during the test, and a dedicated measurement routine was used to prove the recombination of trapped electrons with holes generated by impact ionization. Finally, technological solutions to improve the sustainable breakdown characteristics of the devices are proposed and validated, through the analysis of two different process splits.

An experimental and numerical study of the on-resistance degradation in AlGaN/GaN-based technology is presented. Back-bias measurements on transmission-line-method (TLM) structures were performed to investigate the mechanism underlying the current degradation. The observed TLM current collapse exhibits Arrhenius behavior, which is associated with traps in the buffer layers. Interestingly, the decay time of the collapse shows a decreasing trend with increasing applied bias, which is here investigated and newly interpreted as a signature of Poole–Frenkel bias-enhanced trap emission. An effective model is discussed and implemented in TCAD simulations to support the experimental findings. In addition to providing justification for the temperature and applied-voltage dependence of the observed degradation trends, the proposed mechanism can also explain the spread in the activation energies measured for acceptor traps in the buffer layers, as reported in the literature for AlGaN/GaN technologies.

In this work, we present a comprehensive analysis of the back-effect phenomenon in Schottky p-GaN gate AlGaN/GaN high-electron-mobility transistors (HEMTs). By investigating different device structures, we emphasize the critical role played by the gate terminal in the device’s performance. Our study focuses on two main factors that significantly impact the current degradation caused by the back-effect: the magnesium (Mg) concentration in the p-GaN layer and gate polarization (V ${}_{\text {GS}}\text {)}$ . Finally, we propose a physics-based model supported by experimental data to provide further insights and details into this phenomenon, providing important indication to find the best tradeoff in the development of GaN HEMTs operating in monolithic half-bridge configuration.

In this work, a novel understanding of the main failure mechanism of a Schottky p-GaN gate AlGaN/GaN HEMT subject to forward gate stress is reported. First an experimental characterization of the gate leakage current (I_GSS) at different temperatures is reported. Then, Technology Computer Aided Design (TCAD) simulations are used to reproduce the experimental I_GSS thanks to the impact ionization model, also at different temperatures. Simulation results underline how the stressed regions for the Device Under Test (DUT) at high gate biases are the Schottky/p-GaN interface, the p-GaN/AlGaN barrier interface, and p-GaN sidewalls. Moreover, Time Dependent Gate Breakdown (TDGB) measurements were done, and the TEM analysis on the failed device showed the lattice crystal damage located at the p-GaN/AlGaN interface, in accordance with TCAD simulations’ current density distribution at high voltage gate stress.

In this letter, we investigate the dynamic-R_ON drift of monolithic Bidirectional AIGaN/GaN HEMTs. To this end, a novel measurement setup is proposed to evaluate the impact of the substrate connection. Particularly, (i) grounded and (ii) floating substrate configurations are compared. The partial recovery of the R_ON-degradation at high stress voltage is demonstrated, for the first time, on Bidirectional GaN devices with grounded substrate. Conversely, a higher R_ON-drift is observed with floating substrate configuration, due to the negative back-bias effect experienced during on-state time interval. This extends the knowledge on this topic, providing physical insights into the large degradation observed in previous work by highlighting the detrimental effect of leaving the substrate floating in Bidirectional power switches.

Sustainable avalanche operation was demonstrated and investigated on lateral E-mode GaN HEMT devices with sub-micrometer gate length. Through an extensive analysis: a) we demonstrated that sustainable avalanche operation is made possible by the presence of a subthreshold drain-source leakage, that initiates impact ionization; b) this process clamps the drain voltage to values lower than the dielectric breakdown voltage, thus preventing the catastrophic failure of the devices; c) avalanche operation is sustainable, and the related voltage strongly depends on the device geometry; d) spectrally resolved electroluminescence measurements demonstrate the presence of band-to-band luminescence, ascribed to recombination of holes, generated by impact ionization during the process. Finally, e) the positive temperature coefficient of avalanche voltage has been demonstrated. Support to the interpretation was obtained based on TCAD simulations.

In this paper, the impact of SiN passivation on dynamic-R_ON degradation of AlGaN/GaN HEMTs devices is put in evidence. To this end, samples showing different SiN passivation stoichiometry are considered, labeled as Sample A and Sample B. For dynamic-R_ON tests, two different experimental setups are employed to investigate the R_ON-drift showing up during conventional switch mode operation by driving the DUTs under both (i) resistive load and (ii) soft-switching trajectory. This allows to discern the impact of hot carriers and off-state drain voltage stress on the R_ON parameter drift. Measurements performed with both switching loci shows similar dynamic-R_ON response, indicating that hot carriers are not involved in the degradation of tested devices. Nevertheless, a significant difference was observed between Sample A and Sample B, with the former showing an additional R_ON-degradation mechanism, not present on the latter. This additional drift is totally ascribed to the SiN passivation layer and is confirmed by the different leakage current measured across the two SiN types. The mechanism is explained by the injection of negative charges from the Source Field-Plate towards the AlGaN surface that are captured by surface/dielectric states and partially depletes the 2DEG underneath.

In this brief, we investigate the correlation between dynamic- ${Q}_{\text {OSS}}$ and dynamic- ${R}_{\text {ON}}$ of 650-V packaged AlGaN/GaN high-electron-mobility transistors (HEMTs). To this end, a novel measurement setup is proposed to evaluate the on-the-fly evolution of both parameters during conventional switch-mode operations. The measurements performed at ${V}_{\text {DS}} =200$ V show that the dynamic- ${R}_{\text {ON}}$ and dynamic- ${Q}_{\text {OSS}}$ present similar exponential transients and time constants, potentially explained by the ionization of C-related acceptors in the GaN buffer. The same activation energy ( ${E}_{\text {A}}\text {)}$ has been observed for both ${Q}_{\text {OSS}}$ and ${R}_{\text {ON}}$ , suggesting that their drifts are related to the same physical mechanism. The characterization has also been performed at different ${V}_{\text {DS}}$ levels, indicating that the observed correlation holds in the entire range up to 520 V.

In this paper, preliminary gate reliability of p-GaN HEMTs under high positive gate bias is studied. Gate robustness is of great interest both from an academic and industrial point of view; in fact, different tests and models can be explored to estimate the device lifetime, which must meet some minimum product requirements, as specified by international standards (AEC Q101, JESD47, etc.). However, reliability characterizations are usually time-consuming and are performed in parallel on multiple packaged devices. Therefore, it would be useful to have a faster method to screen out weaker gate trials, already on-wafer, before reaching the packaging step. For this purpose, a room-temperature stress procedure is presented and described in detail. Then, this screening test is applied to devices with a reference gate process, and, as a result, high gate leakage degradation is observed. Afterwards, a different process implementing a dielectric layer between p-GaN and gate metal is evaluated, highlighting the improved behavior during the stress test. However, it is also observed that devices with this process suffer from very high drain leakage, and this effect is then studied and understood through TCAD (technology computer-aided design) simulations. Finally, the effect of a surface treatment performed on the p-GaN is analyzed, showing improved gate pre-reliability while maintaining low drain leakage.

This letter substantially improves the understanding on the degradation of normally-OFF GaN HEMTs with p-GaN gate subject to forward gate stress, and demonstrates that a significant reliability enhancement can be obtained at high bias through hole injection from the gate terminal. Key results are: (i) for the first time we adopt an experimental setup capable of investigating the threshold voltage shift of the devices during time-dependent breakdown tests in a wide time window (from $\mu $ s to failure). (ii) Remarkably, we demonstrate that the acceleration factor for gate breakdown is substantially lower at high stress voltage. (iii) The lower acceleration factor of degradation at high voltages is correlated to the number of holes which are injected and trapped in the gate stack. The results give strong experimental evidence that the injection of holes from the p-GaN contact can have a beneficial effect on device robustness, by reducing – through recombination – the amount of hot electrons responsible for degradation.