Bertrand Parvais

The telecommunications sector is experiencing rapid growth, driven by the exponential rise in data transmission volumes. This demand has led to significant innovation in the front-end-module, and particularly in the power amplifiers (PAs), requiring III–V group-based compound semiconductor materials, instead of traditional silicon-based technologies. ICT hardware manufacturing raises multiple sustainability concerns, including the intensive use of natural resources, significant waste generation, and the high consumption of electrical energy during production. These issues are further exacerbated by the rapid growth of the ICT market and the increasing shift toward non-silicon-based technologies. We address these issues in this paper through a comparative life cycle assessment (LCA) of the environmental impacts associated with the fabrication of PAs based on different semiconductor technologies suited for user equipment applications (45RFSOI, GaN-on-Si HEMT, GaAs HBT). We show a substantially higher impact per cm ² in terms of climate change (∼1.6x higher) and resource depletion (∼470x higher) for the market-dominant GaAs PA compared to RFSOI and GaN-on-Si technologies. It is due to the GaAs wafer manufacturing and the usage of gold. In addition to LCA considerations, the integration of compound semiconductor materials introduces broader sustainability concerns, particularly with respect to resource scarcity, economic viability, and potential social implications. We explore these dimensions and highlight concerns related to gold usage in GaAs PA as well as different critical materials used in these radio frequency technologies.

This article presents an analytical model of the barrier layer in GaN-MISHEMT that predicts a limitation of the channel charge density that is expected to reach an asymptotic value under high gate voltages, a feature that was not reported before. We find that this behavior is very sensitive to the device parameters such as the AlGaN barrier thickness, composition, and polarization-induced charge density. Explicit relationships for charge saturation in the quantum well (QW) are proposed and can be used to optimize GaN-MISHEMT architectures.

This study comprehensively investigates the threshold voltage ( ${V}_{\text {th}}\text {)}$ instability of AlGaN/GaN MIS-HEMTs under semi-bioscon state conditions. The effects of various temperatures and drain biases are studied. Under semi-bioscon bias conditions, a significant negative ${V}_{\text {th}}$ shift up to −1.0 V is observed in MIS-HEMTs with 10-nm in-situ SiN gate dielectrics, whereas Schottky HEMTs exhibit a negligible ${V}_{\text {th}}$ shift. A gate current analysis, comparing the MIS-HEMT with the source grounded versus floating, suggests that hot electrons induce generation of holes under the semi-on state. TCAD simulations corroborate that the high electric field across the channel of the MIS-HEMT induce hot electrons and hole generation under the semi-bioscon state; dynamic interaction of hot electrons and holes with the gate SiN/AlGaN interfacial states leads to bias temperature instability (BTI) of the ${V}_{\text {th}}$ of the MIS-HEMT. These findings suggest that optimizing the gate dielectric and its interface with the top barrier is crucial to improve the semi-bioscon state stability of radio-frequency (RF) MIS-HEMTs.

Most part of electronic devices nowadays make use of System-on-a-Chip (SoC), since it is responsible for a series of performance increments [1,2]. Several of the SoC modules, for example the low-noise amplifier and the power amplifier, can make good use of GaN-based transistors frequency and power parameters [3,4]. GaN-based Metal-Insulator-Semiconductor High Electron Mobility Transistors (MISHEMT) can offer higher current densities, enabling higher power electronics, and higher operation frequencies, due to its electron current channel, a 2-dimensional electron gas (2DEG) generated at its heterostructure interfaces [5,6]. Imec’s recent GaN-on-Si MISHEMTs are capable of offering up to a hundred GHz frequency figures of merit and tens of dB gains [7]. Figure 1 shows the structure of the studied MISHEMT, with 2 nm Si₃N₄ as gate insulator, 10 nm AlGaN as top layer, 1 nm AlN interlayer and 300 μm GaN buffer. The devices were tested using a 100 μm pitch G-S-G RF measurement structure. Figure 2 shows the MISHEMT electron current density as a function of its depth for several gate overdrive voltages (V_GT = V_GS - V_T). For V_GS = V_T there is already current density through the 2DEG on the 3^rd interface. When V_GT = 3.0 V, the current density at the 2^nd interface increases, but it is approximately 2 orders of magnitude lower than the one at the 3^rd interface. With V_GT = 4.0 V the conduction takes place through all the AlGaN layer, presenting higher current densities at the 1^st and 3^rd interfaces. One important remark is that the conduction through the 1^st interface is dependent on the gate to drain underlap region (L_GD), which decreases when the gate to drain electrodes distance increases. Figure 3 (A) shows the drain current of two MISHEMTs with different L_GD, from which can be seen that as higher is V_DS, more pronounced is the I_DS increase at V_GS = V_T, probably due to a stronger 2DEG channel saturation effect. The 2DEG channel is responsible for the first transconductance (g_m) peak showed in Figure 3 (B). Additionally, it can be seen a positive shift in the second g_m peak for increasing V_DS and L_GD, pointing to a gate to drain voltage (V_GD) and a L_GD dependence. For the scattering parameters, the gate is port 1 and drain is port 2. Figure 4 shows the gate reflection coefficient (S₁₁) for MISHEMTs with L_GD = 1.25 and 2.25 μm for different V_GS and V_DS. For a V_DS = 0 V, S₁₁ shows two distinct behaviors, one before electron accumulation in the 1^st interface, with a higher resistance, and one after it, exhibiting lower resistance, since this electron accumulation layer is closer to the gate electrode than the 2DEG. This happens for both devices. Increasing V_DS it can be seen that less distinct becomes the two behaviors previously seen, especially in the shorter device. This is because V_DS, and consequently V_GD, is playing a major role on S₁₁, demonstrating dependence with L_GD. The maximum available gain (MAG) of a transistor is proportional to the ratio between the direct and reverse transmission coefficients, S₂₁ and S₁₂. Despite being known that a shorter device usually shows a better overall performance, in the studied MISHEMT case, as can be seen from S₂₁ and S₁₂ for different bias conditions in Figure 5, a high MAG is expected even for a longer L_GD device if it is biased so that the conduction happen mainly through the 2DEG, due to a high S₂₁ and lower S₁₂. For the shorter device, the electron accumulation layer in the 1^st interface addition to drain current makes the device suitable for a larger frequency and bias range. Figure 1

We discuss a physical mechanism in the AlGaN/GaN high electron mobility transistors (HEMTs) that partial electrons from reverse gate leakage ( $\textit{I}_{\text{g,off}}$ ) inject into the HEMT buffer and thereby shift the HEMT threshold voltage ( $\Delta \textit{V}_{\text{th}}$ ). We analyze the $\Delta \textit{V}_{\text{th}}$ dependences on parameters including gate lengths, front barrier (FB) thickness, gate bias voltage, drain bias voltage, and the distance between the gate and the buffer. We specifically investigate the OFF-state stress with nonzero and zero $\textit{V}_{\text{ds}}$ . The experiment with zero $\textit{V}_{\text{ds}}$ helps identify the $\textit{I}_{\text{g,off}}$ induced C doped GaN (C-GaN) charging; while the one nonzero $\textit{V}_{\text{ds}}$ indicates a fast increase of C-GaN charging induced $\Delta \textit{V}_{\text{th}}$ with $\textit{V}_{\mathbf{ds}}$ . The $\Delta \textit{V}_{\text{th}}$ issue is significant for downscaled HEMTs with a short gate length and a close distance between the gate and the buffer. The issue is thus critical for downscaled HEMTs in high-speed RF applications. We propose a simple analytical expression for the $\Delta \textit{V}_{\text{th}}$ and demonstrate methods to reduce the $\Delta \textit{V}_{\text{th}}$ .

Fabrication of low-RF loss GaN-on-Si high electron mobility transistor stacks is critical to enable competitive front-end-modules for 5G and 6G applications. The main contribution to RF losses is the interface between the III-N layer and the HR Si wafer, more specifically the AlN/Si interface. At this interface, a parasitic surface conduction layer exists in Si, which decreases the substrate effective resistivity sensed by overlying circuitry below the nominal Si resistivity. However, a clear understanding of this interface with control of the parasitic channel is lacking. In this Letter, a detailed physical and electrical description of metalorganic chemical vapor deposition-grown AlN/Si structures is presented. The presence of a SiCxNy interfacial layer is revealed, and its importance for RF losses is shown. Through C–V and I–V characterization, an increase in the C concentration of this interfacial layer is linked to the formation of negative charge at the AlN/Si interface, which counteracts the positive charge present in the 0-predose limit. The variation of the TMAl predose is shown to allow precise tuning of the C composition and, consequently, the resulting interface charge. Notably, a linear relationship between the predose and the net interface charge is observed and confirmed by the fabrication of an AlN/Si sample with close to zero net charge. In addition, a higher Dit (∼2×1012cm−2) for such compensated samples is observed and can contribute to low-RF loss. An exceptionally high effective resistivity of above 8 kΩ cm is achieved, corresponding to an RF loss below 0.3 dB/mm at 10 GHz.