Hao Cui

As electronic devices continue to evolve toward higher power and increased miniaturization, accurate prediction of solder joint life has become increasingly critical for ensuring reliability. Although research in this area dates back to the 1960s and has since produced a wealth of models, establishing a unified life prediction model under multi-field coupling conditions—involving thermal, electrical, and vibration loads—remains challenging due to the distinct damage mechanisms induced by each load type. This paper systematically reviews the applicable scenarios and limitations of existing solder joint life prediction models, classifying them into single-load models and multi-field coupling models. On this basis, a dedicated section summarizes the implementation strategies for multi-field coupled finite element simulations, covering the sequential coupling framework for thermo-electrical and thermo-vibration coupling, as well as the treatment of damage superposition in three-field coupling. A feasible approach that combines the finite element method with machine learning to reduce computational cost is also briefly introduced. Unlike existing reviews, which merely list models, this paper explicitly identifies the core challenges in multi-field coupled life prediction and offers a coherent reference framework—spanning physical modeling, numerical implementation, and data-driven acceleration—to provide guidance for reliability research and engineering design in electronic packaging.

The electronic devices suffer great vibration and temperature fluctuation in an airborne environment, which has been always a big challenge for reliability design. In this paper, the reliability of the complex electronic components for airborne applications under a thermal cycling test, random vibration and combined loading has been investigated by experiment tests and finite element simulation. The fatigue life and failure location under different loadings have been compared and discussed, respectively. The results indicated that the combined fatigue life was much shorter than a single-factor experiment. The failed solder joints mostly appeared at the interface between the solder and the copper pad on the component side and the location was at the corner for all three harsh environment tests. Nevertheless, several differences could be observed. For temperature cycling, all the specimens failed due to the increase in daisy chain resistance rather than the open circuit for the combined loading test. That is because the degeneration of the solder caused by temperature variation led to lower stress levels and fatigue life. Moreover, the pins fractured at the welding regions have been observed. The modified Coffin—Manson model, Miner’s linear fatigue damage criterion and Steinberg’s model and rapid life-prediction approach were used to predict the fatigue life under temperature cycling, random vibration and combined loading, respectively. With these methods, the accurate numerical models could be developed and validated by experiment results. Thanks to the simulation, the design time could be effectively shortened and the weak point could be determined.

With the increasing number of inputs and outputs, and the decreasing interconnection spacing, electrical interconnection failures caused by electromigration (EM) have attracted more and more attention. The electromigration reliability and failure mechanism of complex components were studied in this paper. The failure mechanism and reliability of complex components during the electromigration process were studied through the simulation and the experiment, which can overcome the limitation of experimental measurement at a micro-scale. The simulation results indicated that the solder joint has obvious current crowding at the current inlet, which will significantly enhance the electromigration effect. Based on the atomic flux divergence method, the void formation of solder joints can be effectively predicted, and life prediction can be more accurate than Black’s equation. Experimental results indicated that the resistance of the daisy chain could be significantly increased with the process of void formation in the solder and corrosion of the leads. Moreover, the growth of intermetallic compounds can be obviously promoted under current stress. The main composition of the intermetallic compounds changes from almost entirely Cu₅Sn₆ to Cu₅Sn₆ and Cu₃Sn; the cracks can be detected at the Cu₃Sn layer. Specifically, the mean time to failure is 1065 h under 1.4 A current and 125 °C based on IPC-9701A guidelines.

Intermetallic compound (IMC), as an inevitable part between pad and solder, has a severe effect on the strength and reliability of microelectronic interconnection. Here, an investigation was carried out on IMC growth for different devices and complex components. The device-level experiments were conducted with five factors: peak temperature, time duration above solder liquidus temperature, the thickness of solder paste, surface finish types, and package types including ball grid array (BGA) and quad flat package (QFP). Meanwhile, four complex components with the same reflow profile were conducted and compared for component-level experiments. A scanning electron microscopy (SEM) was used to measure the thickness and determine the spatial distribution of the elements through the IMC. The multivariate analysis of the formation and growth of IMC during reflow soldering was studied based on Nernst–Shchukarev’s equation and the results of the experiments. The difference in IMC thickness between BGA and QFP with different factors was discussed and compared separately. The results showed that the peak temperature and time above liquidus played a vital role in the IMC growth and the solder paste thickness and different pad metallization could not be ignored. SEM pictures of the solder and statistical results were revealed that the surface finish type has a marked impact on the formation of the IMC. For printed circuit board (PCB) with numbers of components, the IMC thickness and uniformity of solder joints at corner and center positions showed some regularity differences. Meanwhile, the bump shape (Cu _{1− x} Ni _x ) ₆ Sn ₅ IMC was observed for small size BGA with electroless nickel and immersion gold during the reflow process. The results have a significant meaning to optimize its reflow process parameters for complex components, to improve the interconnection reliability in engineering.

With the rapid development of 5G, artificial intelligence (AI), and high-performance computing (HPC), there is a huge increase in the data exchanged between the processor and memory. However, the “storage wall” caused by the von Neumann architecture severely limits the computational performance of the system. To efficiently process such large amounts of data and break up the “storage wall”, it is necessary to develop processing-in-memory (PIM) technology. Chiplet combines processor cores and memory chips with advanced packaging technologies, such as 2.5D, 3 dimensions (3D), and fan-out packaging. This improves the quality and bandwidth of signal transmission and alleviates the “storage wall” problem. This paper reviews the Chiplet packaging technology that has achieved the function of PIM in recent years and analyzes some of its application results. First, the research status and development direction of PIM are presented and summarized. Second, the Chiplet packaging technologies that can realize the function of PIM are introduced, which are divided into 2.5D, 3D packaging, and fan-out packaging according to their physical form. Further, the form and characteristics of their implementation of PIM are summarized. Finally, this paper is concluded, and the future development of Chiplet in the field of PIM is discussed.

In order to make the accuracy of temperature control of SIP chips in the aging test not affected by external interference and mathematical models, a paste-adaptive PID temperature control system suitable for the aging test of SIP chips was designed. By analyzing the influence of the changes of the two input variables of temperature deviation and deviation change rate on the aging test temperature, a fuzzy control rule table is established. The influence of control performance is completed, and the simulation and field debugging of the entire fuzzy adaptive PID temperature control scheme are completed. The test results show that the temperature control effect of the burn-in test based on the fuzzy adaptive PID control algorithm is 31.25% higher than that of the conventional PID control algorithm, and the anti-interference performance is improved by 66.6%.

With the rapid development of integrated circuit, 5G, AI and IoT industries, the demand for SIP (System in Package) products is growing rapidly. However, reliability has become the primary challenge for the development of SIP technology. Compared with the traditional package, the SIP circuit has the characteristics of high-power consumption and high internal temperature rise during dynamic operation, so the traditional high temperature test chamber and aging test method cannot meet its test requirements. In this paper, a dynamic aging test scheme based on self-heating is designed for SiP circuit, and an automatic test system without convention high temperature aging test chamber is built. According to the requirements of dynamic aging in GJB548 standard, the results show that the chip surface temperature can be accurately controlled at 85 °C within the range of 0~3°C. The automatic monitoring of aging test status is realized, which ensures the safety of aging test and improves the test efficiency. It also provides an application case for the aging test of the same type of chips.

This paper aims to investigate the atomic migration voids formation and time-to-failure mechanism of Ball Grid Array (BGA) device. In order to analyze the parameter changes of BGA device, the actual model and corresponding equivalent model are established by using ANSYS Workbench software. In this study, the effect of various migration forces on atomic migration is determined, while the migration divergence calculated by migration force predicts the failure time of solder joints. Conclusions are made that the solder joints at the corners failed faster than those in the center, and migration caused by current crowding is the major reason for atomic migration, stress migration accelerates the process and thermal migration has little effect.

In this paper a method of research for the reliability of solder joint shapes is proposed. By using Surface Evolver software, finite element analysis, minimum energy principle and gradient descent method to calculate the minimum state of energy, the final shape of the solder joint is predicted. By studying the shape of SOP solder joints and using Surface Evolver software, the error between model parameters and slice parameters is finally less than ±10%, which reduces the error between device models and slices. The reliability and life of solder joints are more accurately predicted.