Stanley Cheung

In this work, we introduce a non‐volatile heterogeneous quantum dot (QD) III‐V/Al ₂ O ₃ /Si distributed feedback (DFB) laser exhibiting optical memristive behavior. The device operates in the O‐band (∼1300 nm) with a threshold current density of 234 A/cm ² and a side‐mode suppression ratio exceeding 48 dB. Co‐integrated Al ₂ O ₃ ‐based memristors produce bipolar resistive switching, yielding non‐volatile wavelength shifts of ∼46 pm and ∼ 17 dB peak power contrast with zero static holding power. The III‐V/Al ₂ O ₃ /Si heterojunction memristor I – V hysteresis is also modeled. This new device enables simultaneous coherent light generation and persistent optical state storage, establishing a new class of active photonic memory for neuromorphic and reconfigurable wavelength division multiplexing (WDM) applications.

Photonic integrated circuits (PICs) are rapidly increasing in scale and routing complexity, driven by photonic computing, optical switching, programmable interferometer meshes, wavelength-routed optical networks-on-chip, and chip-to-chip optical interconnects. Manual waveguide planning becomes increasingly impractical as designs approach hundreds to thousands of photonic components, because routing must satisfy geometric, optical, electrical, and manufacturing constraints. This paper presents Photonic Routing Optimization and Placement Engine (PROPEL) , a memory-driven, native-accelerated adaptive vector-flow-field routing framework with process-aware waveguide generation for large-scale PIC physical design. PROPEL builds a routing kernel based on a bounded vector-flow-field algorithm and design-rule checking (DRC) validation. The same kernel supports passive optical routing, active optical–electrical routing, and topology-driven net assignment. C++ accelerates computationally intensive field and routing calculations, while Python performs detailed DRC replay, legality checking, route commitment, and GDSFactory-based geometry generation. Compared with state-of-the-art routing solutions, PROPEL is faster on 17 of 18 shared passive-routing cases, with a median speedup of 2.6 × and a geometric-mean speedup of 2.5 ×, while maintaining zero final design-rule violations. PROPEL also supports active optical–electrical routing, topology-driven net assignment, length, delay, and optical-path-length matching, process-map-aware waveguide generation, route-memory reuse, selective rip-up/reroute, and Graphic Data System (GDSII)-level legality replay. These capabilities address heterogeneous PIC layouts where optical, electrical, process, topology, matching, and manufacturability constraints must be handled together. In incremental-layout experiments, PROPEL restores more than 95% of previously verified routes after small local component movements and reroutes only the affected subset, reducing modified-design routing from tens or hundreds of seconds to a few seconds while maintaining zero final design-rule violations.

In this work, we report on the design strategies and experimental validation of ultra-low threshold (2 mW (at 10°C) for 1.3 μm emission. The multi-dimensional design exploration allows for the demonstration of record wall-plug efficiencies (∼10 % ) and threshold current densities (109 A/ cm ² ) among electrically driven, silicon-waveguide-coupled microring lasers. We also demonstrate the thermal performance of several designs with record characteristic temperature values of T ₀ =212 K, indicating minimal temperature dependence of the threshold current. In addition, the high differential gain allows for the demonstration of 3 dB bandwidths up to 5 GHz.

Silicon photonics has emerged as a transformative solution to address the energy and bandwidth challenges of modern computing and communication systems. While integrating diverse materials with silicon has enhanced the functionality of photonic integrated circuits, these hybrid approaches often face challenges related to scalability, cost, and compatibility with CMOS processes. We provide a comprehensive perspective on advancing high-performance all-silicon photonic devices and systems. By fully leveraging the inherent potential of silicon, diverse functionalities have been demonstrated, including Raman lasers, modulators, photodiodes, and optical memories. This approach outlines a pathway toward fully integrated electronic–photonic circuits on the silicon platform, seamlessly aligned with the existing CMOS infrastructure.

In this work, we introduce programmable memory elements embedded within III-V/Si light sources which facilitate non-volatile wavelength tuning. These non-volatile III-V/Si micro-ring lasers (MRLs) exhibit non-volatile wavelength shifts of ~80 pm with ~40 dB signal extinction ratio while consuming 0 electrical static tuning power. An array of 5 cascaded MRLs is demonstrated with each laser capable of 4 programmable non-volatile states, thus yielding 1024 unique states altogether. Write/erase operations were performed up to 100 cycles with non-volatile time duration lasting up to 24 h. These non-volatile lasers are used to demonstrate optical ternary content-addressable memories (O-TCAM) which can find utility in fast memory search and in-memory computing functions necessary for various machine learning algorithms. The end-to-end energy consumption of the non-volatile MRL O-TCAM with 5 ternary symbols is 1156 fJ/sym. This work provides an opportunity for realizing photonic memory applications in next generation non-volatile photonic systems.

Implementing on-chip non-volatile optical memories has long been an actively pursued goal, promising significant enhancements in the capability and energy efficiency of photonic integrated circuits. Here, we demonstrate an non-volatile optical memory exclusively using the most common semiconductor material, silicon. By manipulating the photon avalanche effect, we introduce a trapping effect at the silicon-silicon oxide interface, which in turn demonstrates a non-volatile reprogrammable optical memory cell with a record-high 4-bit encoding, robust retention and endurance. This silicon avalanche-induced trapping memory provides a distinctively cost-efficient and high-reliability route to realize optical data storage in standard silicon foundry processes. We demonstrate its applications in trimming in optical interconnects and in-memory computing. Our in-memory computing test case reduces energy consumption by approximately 83% compared to conventional optical approaches.

This roadmap consolidates recent advances while exploring emerging applications, reflecting the remarkable diversity of hardware platforms, neuromorphic concepts, and implementation philosophies reported in the field. It emphasizes the critical role of cross-disciplinary collaboration in this rapidly evolving field.

The convergence of deep learning and Big Data has spurred significant interest in developing novel hardware that can run large artificial intelligence (AI) workloads more efficiently. Over the last several years, silicon photonics has emerged as a disruptive technology for next-generation accelerators for machine learning (ML). More recently, the heterogeneous integration of III-V compound semiconductors has opened the door to integrating lasers and semiconductor optical amplifiers at wafer-scale, enabling the scaling of the size, density, and complexity of silicon photonic integrated circuits (PICs). Furthermore, using this technology, all of the individual components required to execute the operations within a neural network are available and can be integrated on the same PIC. Here, we review our innovations of an energy-efficient and scalable silicon photonic platform serving as the underlying foundation for next-generation AI accelerator hardware.

We explore the use of non-volatile III-V/Si ring lasers as storage elements in wavelength-division multiplexed (WDM) optical ternary content-addressable memory (O-TCAM) search. This provides new opportunity for photonic memory applications in non-volatile photonic systems.