Katsumi Abe

We confirmed that quantum confinement effects are clearly observed even in a disordered material. Employing amorphous In–Ga–Zn–O (a-IGZO) thin-film transistors (TFTs) with quantum well channels, it was observed that field-effect mobility–gate voltage relations exhibited plateaus when the well thickness was 5 nm or less. Device simulation incorporating the quantum confinement effects reproduced the well-thickness dependence of the plateau onset voltage, verifying that the quantized electronic levels in the a-IGZO well dominate the TFT characteristics and, thus, the electron transport is free electron like with a coherent length of ∼5 nm. The field-effect mobility did not exceed the drift mobility of bulk a-IGZO, which is different from amorphous silicon superlattice TFT.

As novel applications of oxide semiconductors are realized, various structural devices and integrated circuits are being proposed, and the gate-overlay defect phenomenon is becoming more diverse in its effects. Herein, the electrical properties of the transistor that depend on the geometry between the gate and the semiconductor layer are analyzed, and the specific phenomena associated with the degree of overlap are reproduced. In the semiconductor layer, where the gate electrode is not overlapped, it is experimentally shown that a dual current is generated, and the results of 3D simulations confirm that the magnitude of the current increases as the parasitic current moves away from the gate electrode. The generation and path of the parasitic current are then represented visually through laser-enhanced 2D transport measurements; consequently, the flow of the dual current in the transistor is verified to be induced by the electrical potential imbalance in the semiconductor active layer, where the gate electrodes do not overlap.

The reduction in current ability accompanied by the hump phenomenon in oxide semiconductor thin-film transistors to which high DC voltages and AC drive voltages are applied has not been studied extensively, although it is a significant bottleneck in the manufacture of integrated circuits. Here, we report on the origin of the hump and current drop in reliability tests caused by the degradation in the oxide semiconductor during a circuit driving test. The hump phenomenon and current drop according to two different driving stresses were verified. Through a numerical computational simulation, we confirmed that this issue can be caused by an additional “needle”, a shallow (~0.2 eV) and narrow (<0.1 eV), defect state near the conduction band minimum (CBM). This is also discussed in terms of the dual current path caused by leakage current in the channel edge.

Device models of amorphous oxide semiconductor thin-film transistors (AOS TFTs) associate AOS carrier transport and electronic states with AOS TFT electrical characteristics. Thus, such models are very useful for estimation and analysis on operations and reliability of AOS TFTs and developments of electronic devices with AOS TFTs. We discuss the models including mobility models and density of subgap state (DOS) models, which reflect the carrier-electron transport and the electronic states of AOSs. A device simulator employing a carrier-electron density dependent mobility model and an appropriate DOS model can reproduce temperature and electrical characteristics of AOS TFTs.

Asymmetrical electrical properties induced by local acceptor-like defect states in oxide semiconductor thin-film transistors are investigated. In addition, we report on the origin of asymmetrical transport characteristics depending on the drain voltage level. In particular, we observe that these asymmetrical properties depend strongly on this level. Numerical calculations demonstrate that potential barrier lowering in the local area occurs at the drain electrode's edge.

Defect generation in oxide semiconductor thin-film transistors under high-voltage driving has not been studied in depth despite being a crucial bottleneck in the making of the integrated circuit utilized in an oxide semiconductor. Here we report on the origin of the asymmetrical transport characteristics caused by the degradation in the oxide semiconductor during integrated circuit driving. The variation of the current profiles based on test conditions is related to the generation of local defect states in the oxide material; this generation could be caused by the structural change of the material. The numerical calculations show that the flow of the electron is blocked by the “electrical pocket” formed by the electric-field distortion due to the local defect states near the edge of the electrode.

Reliability issues associated with driving metal-oxide semiconductor thin film transistors (TFTs), which may arise from various sequential drain/gate pulse voltage stresses and/or certain environmental parameters, have not received much attention due to the competing desire to characterise the shift in the transistor characteristics caused by gate charging. In this paper, we report on the reliability of these devices under AC bias stress conditions because this is one of the major sources of failure. In our analysis, we investigate the effects of the driving frequency, pulse shape, strength of the applied electric field, and channel current, and the results are compared with those from a general reliability test in which the devices were subjected to negative/positive bias, temperature, and illumination stresses, which are known to cause the most stress to oxide semiconductor TFTs. We also report on the key factors that affect the sub-gap defect states, and suggest a possible origin of the current degradation observed with an AC drive. Circuit designers should apply a similar discovery and analysis method to ensure the reliable design of integrated circuits with oxide semiconductor devices, such as the gate driver circuits used in display devices.

The effect of an ambient atmosphere with a positive bias constant current stress (CCS) and a negative bias illumination stress (NBIS) on the stability of amorphous In-Ga-Zn-O thin film transistors (TFTs) is examined by utilizing a glass-hermetic-sealant with a moisture permeability of less than 10⁻⁶ g/m² · day. In the CCS test, the threshold voltage shift (ΔV_th) was remarkably suppressed in the glass-sealed TFTs. The unsealed and resin-sealed TFTs exhibited large ΔV_th values. During the NBIS tests, the glass-sealed TFTs had almost the same negative ΔV_th as the unsealed and resin sealed TFTs. Among the different TFTs, no significant differences were observed in the threshold voltage, the subthreshold swing and the saturation mobility as a function of the photon energy. It is concluded that ambient molecules were the primary origin of the instability of the ΔV_th, induced by a CCS, but they were not related to the NBIS instability. The major role of the effective passivation layers in the NBIS test was not to simply block out the ambient effects, but to reduce the extra density of states at/near the surface of the back channel.