Pakpoom Hoyingcharoen
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Pakpoom Hoyingcharoen has a total of 7 co-authors. Here are the top co-authors by number of shared publications:
- Apidet Booranawong
Prince of Songkla University
2 shared publications - Kiattisak Sengchuai
Prince of Songkla University
2 shared publications Masami Ikura
Toyota Tsusho Nexty Electronics (Thailand) co, Ltd Bangkok, Thailand
2 shared publications- Nattha Jindapetch
Prince of Songkla University
2 shared publications Panadda Solod
Department of Electrical Engineering, Faculty of Engineering, Prince of Songkla University, Hat Yai, Songkhla 90112, Thailand
2 shared publicationsSurachate Chumpol
Toyota Tsusho Nexty Electronics (Thailand) co, Ltd Bangkok, Thailand
2 shared publications
Latest Publications
- Open Access
- 30 April 2021
- Published by Universiti Putra Malaysia in Pertanika Journal of Science and Technology
- Vol. 29 (2) , 707-724
High Level Synthesis Optimizations of Road Lane Detection Development on Zynq-7000
Pertanika Journal information and guidelines
- 30 April 2021
- Published by Universiti Putra Malaysia in Pertanika Journal of Science and Technology
- Vol. 29 (2) , 707-724
Open AccessHigh Level Synthesis Optimizations of Road Lane Detection Development on Zynq-7000
Pertanika Journal information and guidelines
- 1 September 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
Memory Optimization for Accelerating Hough Transform on FPGA using High Level Synthesis
In this work, we present memory optimization in Hough transform on hardware of programmable logic (PL) part of FPGAs by using array partitioning block, cyclic and complete types at different dimension and different factor on the Xilinx Vivado High Level Synthesis tool. Loop analysis was presented to extract nested loops and suitably manage the array. The experimental results show that adding array partitioning complete type at dimension 2 can be the best type to improve speed of operating time and reduce the number of resources on Zybo ZC7010-1.
- 1 September 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
Memory Optimization for Accelerating Hough Transform on FPGA using High Level Synthesis
In this work, we present memory optimization in Hough transform on hardware of programmable logic (PL) part of FPGAs by using array partitioning block, cyclic and complete types at different dimension and different factor on the Xilinx Vivado High Level Synthesis tool. Loop analysis was presented to extract nested loops and suitably manage the array. The experimental results show that adding array partitioning complete type at dimension 2 can be the best type to improve speed of operating time and reduce the number of resources on Zybo ZC7010-1.
- 26 February 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Sensors Journal
- Vol. 19 (12) , 4480-4493
Expected Probabilistic Detection and Sink Connectivity in Wireless Sensor Networks
- 26 February 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Sensors Journal
- Vol. 19 (12) , 4480-4493
Expected Probabilistic Detection and Sink Connectivity in Wireless Sensor Networks