Weilin Xu

For low-power Internet of Things (IoT) applications, an Envelope Detector-First (ED-first) architecture ultra-low-power wake-up receiver in 65 nm CMOS technology is presented. Based on the analysis of the sensitivity constraint mechanism of this wake-up receiver architecture, a five-order passive differential envelope detector with high input impedance is introduced to replace the traditional active envelope detector, which was optimized to reduce power consumption and improve the sensitivity of the receiver. A common-mode feedback circuit detects the bias voltage of the current-reusing inverter-based BB amplifier, achieving regulation of the ED’s common-mode level and BB amplifier bias, making the system insensitive to PVT variations. When operating at 850 MHz and receiving a 200-bps data rate wake-up signal, the receiver has a [Formula: see text]74 dBm sensitivity with a 58 ms latency while consuming 12.8 nW from the 0.4 V supply, and the Figure of Merit (FoM) value is 145.9.

This paper presents a hybrid buck-boost DC-DC converter structure to address the limitations of single-output and low conversion ratios (CR) in traditional energy harvesting systems. To reduce the CR of the inductive boost and enhance the total CR of the converter while improving efficiency, the proposed converter cascades a boost circuit with a reconfigurable switched capacitor (SC), and also includes a supercapacitor. The advantage of this architecture is the ability to use low-voltage low-threshold transistors with lower parasitic capacitance and on-resistance, which achieve high-voltage output while reducing switching and conduction losses. The supercapacitor can store energy under a light load and provide additional energy replenishment in buck mode under heavy load. The reconfigurable SC circuit can enable a 2V or 3V output by configuring the switch array. Adaptive switching frequency control was used to achieve a balance between load capability and switching loss. The proposed DC-DC converter is designed with a 0.18 µm CMOS process and has maximum conversion efficiencies of 91.83%, 89.42%, and 88.09% for the inductive boost stage, 2V SC output stage, and 3V SC output stage, respectively. The output voltage ripple is less than 20 mV at 1V output and less than 30 mV at 2V output and 3V output. The input voltage of the converter is as low as 20 mV. The converter features multi-output, high-conversion-ratio, and enhanced efficiency, which are suitable for energy-harvesting applications.

This paper presents a level-crossing successive-approximation-register (LC-SAR) hybrid analog-to-digital converter (ADC) that combines an LC ADC with an SAR ADC, which may be used for Internet of Things (IoT) random sparse event scenarios. The sampling frequency of a traditional LC ADC is usually proportional to the maximum instantaneous rate of change of the input signal; therefore, a higher input signal frequency inevitably leads to higher system power consumption. However, the proposed hybrid ADC uses the input level difference between the two moments before and after level-crossing detection, thereby ensuring a higher conversion precision and lower power consumption, even at higher input signal frequencies. Compared with traditional LC ADC or SAR ADC, the proposed hybrid ADC combines the ultralow-power advantage of LC ADC with the high-precision advantage of SAR ADC in converting IoT data with sparse characteristics such as ECG, EEG, and brain potential. The LC-SAR hybrid ADC is designed with a 0.18 μm CMOS process and consumes 4.34 μW at a 1.8 V supply voltage, achieving an SNDR of 67.41 dB and a bandwidth of 20 kHz. The spectrum analysis result was 10.85 ENOB when the input sinusoidal signal was 14.975 kHz. When inputted with an ECG signal, the system power consumption was as low as 0.49 μW. Furthermore, the proposed hybrid ADC obtained a good figure of merit, with FoMw and FoMs reaching 58.8 fJ/conv.steps and 164 dB, respectively. Compared to a conventional uniform sampling ADC, approximately 80% of the power savings and an 8x compression ratio can be achieved in physiological signal acquisition applications.

A digital adaptive mismatch calibration (DAMC) circuit is proposed to decrease the output jitter of phase-locked loop (PLL). After amplifying the phase error with a linear time amplifier (TA), the DAMC adopts a successive approximation pulse width calibration method to reduce the mismatch current of the charge pump. The PLL prototype is fabricated in a 40nm process, the static phase error of the proposed PLL can be reduced from 358 ps to 10 ps at a 50 MHz reference clock approximately, and the RMS jitter of the PLL output is reduced from 4.91 ps to 3.59 ps, and the extended DAMC area only occupies 1.3% of the whole PLL area.

The scattering enhancement technique has shown prominent potential in various regimes such as satellite communication, Radar Cross Section (RCS) camouflage, and remote sensing. Currently, the scattering enhancement devices based on the metasurface have shown advantages in light weight and better performance. These metasurfaces always possess complex structure, it is hard to achieve through the tradition trial-and-error method which relies on the full-wave numerical simulation. In this paper, a new method combining the machine learning and the evolution optimization algorithm is proposed to design the metasurface retroreflector (MRF) for arbitrary direction incident wave. In this method, a predicting model and a generative inverse design model are constructed and trained, the predicting model is used to evaluate the fitness of each offspring in the genetic algorithm (GA), the generative model is used to initialize the first offspring of the GA by inverse generate the MRF based on the requirements of the designer. With the assistance of these two machine learning models, the evolution optimization algorithm is employed to find the optimal design of the MRF. This approach enables automatic solution of electromagnetic inverse design problems and opens the way to facilitate the optimization of other metadevices.

Most conventional memristor-based Pavlov associative memory neural network circuits have been working on realizing the learning and forgetting functions of simultaneous conditioning. However, the time interval between unconditional stimulus and conditional stimulus is a critical variable in classical conditioning. Different unconditional and conditional stimulus intervals evoke associative memory of brains with different rates. For example, learning in simultaneous conditioning is less effective than delay conditioning. Therefore, a memristor-based neural network circuit of delay and simultaneous conditioning is designed. The proposed circuit consists of learning states detection module, voltage control module, and synapse module. Many functions, such as short-delay conditioning learning, long-delay conditioning learning, simultaneous conditioning learning, experience learning, and two types of forgetting are implemented by the circuit. In particular, the so-called experience learning is that learning the forgotten knowledge will be faster than before and learning again will forget more slowly. This function is more bionic. The correctness of the design is demonstrated through simulations using PSPICE.

The rapid development of artificial intelligence (AI), big data analytics, cloud computing, and Internet of Things applications expect the emerging memristor devices and their hardware systems to solve massive data calculation with low power consumption and small chip area. This paper provides an overview of memristor device characteristics, models, synapse circuits, and neural network applications, especially for artificial neural networks and spiking neural networks. It also provides research summaries, comparisons, limitations, challenges, and future work opportunities.

Actively controlling the amplitude and phase of terahertz (THz) wave is of great significance for THz broadband wireless communication and high-resolution THz imaging. In this paper, we present a THz amplitude and phase modulator based on electrically triggered vanadium dioxide (VO ₂ ) reconfigurable metasurface. The unit cell of the device consists of three concentric split-rings-rings (SRRs) on the sapphire substrate, i.e., one VO ₂ -split-ring (VSR) and two metal SRRs. The VSR is embedded between two metal SRRs. The resonance mode, resonance intensity and surface current distribution in the unit cell can be dynamically manipulated by electrically triggering the insulator-to-metal-transition (IMT) of the VO ₂ . The sample is fabricated using a surface micromachining process and characterized by a THz time-domain-spectroscopy (TDS) system. The experimental results show that, 90 degrees phase shift is achieved in a broad bandwidth of 70 GHz. Meanwhile, the amplitude modulation depth reaches 71% at 0.79 THz. The transmission and the phase shift are calculated by an equivalent circuit model, and simultaneously simulated using a full-wave circuit simulation software based on the Method of Moments (MoM). The calculation and simulation results agree with the experimental results. The device has potential applications in THz imaging, broadband wireless communications and array phase controlling.