Daehyeok Kim
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Daehyeok Kim has a total of 7 co-authors. Here are the top co-authors by number of shared publications:
- Minkyu Song
Department of Semiconductor Science, Dongguk University, Seoul 100-715, Korea
3 shared publications - Byeongseong Choe
Department of Information and Telecommunication Engineering, Dongguk University-Seoul, Seoul 04620, Korea
1 shared publication - Jaeyoung Bae
Department of Semiconductor Science, Dongguk University, Seoul 100-715, Korea
1 shared publication - Mun-Kyo Lee
Yongin Research Institute, Hanwha Systems, Daejeon 17121, Gyeonggi-do, Republic of Korea
1 shared publication - Soo Youn Kim
Department of System Semiconductor, Dongguk University, Seoul 04620, Republic of Korea
1 shared publication - Sun-Phil Nah
Agency for Defense Development
1 shared publication
Latest Publications
- Open Access
A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems
In this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 μm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS) is 4.4 μm × 4.4 μm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution) with supply voltages of 3.3 V (analog) and 1.8 V (digital) and 14 frame/s of frame rates.
Open AccessA Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems
In this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 μm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS) is 4.4 μm × 4.4 μm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution) with supply voltages of 3.3 V (analog) and 1.8 V (digital) and 14 frame/s of frame rates.
- 19 January 2016
- Published by Springer Nature in Analog Integrated Circuits and Signal Processing
- Vol. 86 (3) , 407-415
An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique
- 19 January 2016
- Published by Springer Nature in Analog Integrated Circuits and Signal Processing
- Vol. 86 (3) , 407-415
An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique
- Open Access
A High Speed CMOS Image Sensor with a Novel Digital Correlated Double Sampling and a Differential Difference Amplifier
In order to increase the operating speed of a CMOS image sensor (CIS), a new technique of digital correlated double sampling (CDS) is described. In general, the fixed pattern noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA) that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 µm CIS technology and it has the VGA resolution of 640 × 480. The measured conversion time is 16 µs, and a high frame rate of 131 fps is achieved at the VGA resolution.
Open AccessA High Speed CMOS Image Sensor with a Novel Digital Correlated Double Sampling and a Differential Difference Amplifier
In order to increase the operating speed of a CMOS image sensor (CIS), a new technique of digital correlated double sampling (CDS) is described. In general, the fixed pattern noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA) that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 µm CIS technology and it has the VGA resolution of 640 × 480. The measured conversion time is 16 µs, and a high frame rate of 131 fps is achieved at the VGA resolution.