Jiezhi Chen

Advancing ultrahigh-density 3-D ferroelectric random-access memory (FeRAM) integration, we demonstrate excellent thickness scalability in fully ALD-deposited metal–ferroelectric–metal (MFM) stacks consisting of 3-nm TiN/3-nm HZO/3-nm TiN. These ultrathin devices exhibit robust ferroelectricity ( $2{P}_{\text {r}} \gt 22~{\mu }$ C/cm ${}^{{2}}\text {)}$ together with a record-low coercive voltage ( $2{V}_{\text {c}} \lt 0.65$ V). This breakthrough is enabled by a polycrystalline-to-amorphous transition in the TiN electrodes that occurs as they are thinned. This thickness-driven amorphization reduces the lattice mismatch with the ferroelectric o-phase, thereby promoting o-phase formation in HZO and enabling simultaneous downscaling of both HZO and TiN layers. Beyond reducing the overall stack thickness, thinner TiN electrodes also enhance reliability by providing smoother interfaces and suppressing oxygen scavenging, which together minimize leakage and increase breakdown strength. As a result, our ultrathin capacitors set several benchmarks for 3-nm ferroelectric layers, achieving an ultralow leakage current ( ${I}_{\text {leakage}} \lt 10^{-{3}}$ A/cm² at 3 MV/cm), an ultrahigh breakdown field ( ${E}_{\text {BD}} \gt 9.5$ MV/cm), and durable endurance ( $\gt 10^{{11}}$ cycles) without ferroelectric failure (final $2{P}_{\text {r}} \gt 18~{\mu }$ C/cm² and no electrical breakdown). Our work offers critical insights and unlocks new possibilities for pushing the boundaries of high-performance, ultradense, and low-power 3-D ferroelectric memories.

To gain deeper insights into the impact of strain engineering on monolayer (ML) p-type oxide semiconductor Tin monoxide (SnO) and its device performance, we conducted a comprehensive investigation using first-principles calculations. Uniaxial strain was applied to ML SnO to enhance the on-state current (Ion) in devices. First, we analyzed the strain-induced modifications in the band structure, Bloch states, and effective mass of SnO, highlighting the potential for improved hole mobility. Subsequently, double-gate field-effect transistors (DG FETs) with channel lengths (LCh) ranging from 1 to 5 nm were simulated to evaluate the impact of strain on device characteristics. The results demonstrate that applying strain to ML SnO effectively increases Ion and reduces the subthreshold swing, establishing strain engineering as a promising strategy for enhancing the performance of ML SnO-based DG FETs.