Xin Du
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Xin Du has a total of 92 co-authors. Here are the top co-authors by number of shared publications:
- Zhihui Lu
College of Computer Science and Artificial Intelligence, Fudan University, Shanghai, China
11 shared publications - Shuiguang Deng
Zhejiang University, Hangzhou, China
9 shared publications - Gang Pan
College of Computer Science and Technology, Zhejiang University, Hangzhou, Zhejiang, China
7 shared publications - Qiang Duan
Information Sciences & Technology Department, Pennsylvania State University, Abington, PA 19001, USA
6 shared publications - Ouwen Jin
Zhejiang University, Hangzhou, China
5 shared publications - Qinghui Xing
Zhejiang University, Hangzhou, China
5 shared publications
Latest Publications
- Open Access
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
UniSpike: Accelerating Spiking Neural Networks on Neuromorphic Systems via Eliminating Address Redundancy
Many-core neuromorphic systems serve as specialized accelerators for Spiking Neural Networks (SNNs). However, the communication mechanisms in existing neuromorphic systems incur significant traffic and energy overhead due to redundant address transmissions, a bottleneck exacerbated by the short payloads inherent to the spike-based communication nature of SNNs. Specifically, our characterization reveals that in current neuromorphic systems, duplicate address transmissions can account for up to 49% of the total traffic in representative workloads. This paper presents UniSpike, a hardware-software co-design that eliminates address redundancy by aggregating spikes destined for the same core into single, compact packets. UniSpike implements a spike transmission scheduling strategy to enable efficient spike merging, supported by a dedicated hardware architecture for runtime packet assembly and dispatch, as well as a destination-aware SNN partitioning algorithm that maximizes address sharing opportunities. Experimental results demonstrate that on average, UniSpike reduces traffic volume by 1.93×, achieving 1.77× speedup and 1.50× energy efficiency improvement over SOTA designs.
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Open AccessUniSpike: Accelerating Spiking Neural Networks on Neuromorphic Systems via Eliminating Address Redundancy
Many-core neuromorphic systems serve as specialized accelerators for Spiking Neural Networks (SNNs). However, the communication mechanisms in existing neuromorphic systems incur significant traffic and energy overhead due to redundant address transmissions, a bottleneck exacerbated by the short payloads inherent to the spike-based communication nature of SNNs. Specifically, our characterization reveals that in current neuromorphic systems, duplicate address transmissions can account for up to 49% of the total traffic in representative workloads. This paper presents UniSpike, a hardware-software co-design that eliminates address redundancy by aggregating spikes destined for the same core into single, compact packets. UniSpike implements a spike transmission scheduling strategy to enable efficient spike merging, supported by a dedicated hardware architecture for runtime packet assembly and dispatch, as well as a destination-aware SNN partitioning algorithm that maximizes address sharing opportunities. Experimental results demonstrate that on average, UniSpike reduces traffic volume by 1.93×, achieving 1.77× speedup and 1.50× energy efficiency improvement over SOTA designs.
- Open Access
- 12 April 2026
- Published by Association for Computing Machinery (ACM)
- p. 5063-5074
MASI: Memory-Adaptive Inference Framework for Spiking Neural Networks on Edge Devices
- 12 April 2026
- Published by Association for Computing Machinery (ACM)
- p. 5063-5074
Open AccessMASI: Memory-Adaptive Inference Framework for Spiking Neural Networks on Edge Devices
- 26 December 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. PP  (02780070) , 1
SNNcut: An Efficient Partitioning Method for Large-Scale Spiking Neural Networks Using Spike-Sharing
Neuromorphic systems, designed to execute Spiking Neural Networks (SNNs) efficiently, feature a many-core architecture equipped with a Network-on-Chip (NoC) to facilitate spike communication. The distributed memory and decentralized computation require partitioning SNNs into multiple subnetworks, each executed on a neuromorphic core in parallel. However, the increasing scale of SNNs leads to high inter-core spike traffic and expensive computational cost of partitioning algorithms. To address these challenges, we propose SNNcut, an efficient partitioning method for large-scale SNNs using spike-sharing. This approach fully exploits spike-sharing by using one NoC packet to deliver multiple spikes of information to reduce spike traffic. Meanwhile, instead of exhaustively searching over neurons in SNN, SNNcut indexes neurons based on the layer connection pattern and clusters sequentially, which significantly reduces the computational complexity and ensures the efficiency of large-scale SNN partitioning. Experimental results demonstrate that SNNcut achieves an average reduction in spike traffic of 98.97%, compared to 74.98% from state-of-the-art existing methods. In addition, the SNNs partitioned by SNNcut require only 5.7%∼15.7% neuromorphic core consumption of previous works. In a large-scale scenario, existing methods take more than 100 hours to accomplish the partitioning, while SNNcut only needs 10 minutes. We also validate the scalability of SNNcut by testing on edge cases with 3.2B neurons and 902B synapses.
- 26 December 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. PP  (02780070) , 1
SNNcut: An Efficient Partitioning Method for Large-Scale Spiking Neural Networks Using Spike-Sharing
Neuromorphic systems, designed to execute Spiking Neural Networks (SNNs) efficiently, feature a many-core architecture equipped with a Network-on-Chip (NoC) to facilitate spike communication. The distributed memory and decentralized computation require partitioning SNNs into multiple subnetworks, each executed on a neuromorphic core in parallel. However, the increasing scale of SNNs leads to high inter-core spike traffic and expensive computational cost of partitioning algorithms. To address these challenges, we propose SNNcut, an efficient partitioning method for large-scale SNNs using spike-sharing. This approach fully exploits spike-sharing by using one NoC packet to deliver multiple spikes of information to reduce spike traffic. Meanwhile, instead of exhaustively searching over neurons in SNN, SNNcut indexes neurons based on the layer connection pattern and clusters sequentially, which significantly reduces the computational complexity and ensures the efficiency of large-scale SNN partitioning. Experimental results demonstrate that SNNcut achieves an average reduction in spike traffic of 98.97%, compared to 74.98% from state-of-the-art existing methods. In addition, the SNNs partitioned by SNNcut require only 5.7%∼15.7% neuromorphic core consumption of previous works. In a large-scale scenario, existing methods take more than 100 hours to accomplish the partitioning, while SNNcut only needs 10 minutes. We also validate the scalability of SNNcut by testing on edge cases with 3.2B neurons and 902B synapses.
- 25 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Intelligent Systems
- Vol. 41  (3) , 23-34
SNNL: A Programming Language for Spiking Neural Network Development
Spiking Neural Networks (SNNs) are gaining attention for biological plausibility and energy efficiency. Advances in neuromorphic systems—integrating hardware and software tools—accelerate SNN implementation. Yet, deploying SNNs on such platforms remains challenging due to model complexity and system heterogeneity, requiring flexible frameworks. Existing tools (e.g., PyNN, Brian2) show limited expressiveness for neuromorphic applications or poor cross-platform support. This paper proposes SNNL, a flexible domain-specific language for SNN development and deployment on neuromorphic hardware. SNNL decouples neuronal dynamics modeling from network topology specification: equation-based representations handle diverse neuron/synapse models, while hierarchical constructs define complex connectivity patterns. We present a Darwin3-targeted compiler with efficient code generation. Evaluations confirm SNNL achieves precise neuronal dynamic descriptions and flexible network configurations. This work bridges algorithm-hardware gaps in neuromorphic computing by enhancing programmability. Experimental results have demonstrated the feasibility of SNNL in developing SNNs for neuromorphic systems.
- 25 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Intelligent Systems
- Vol. 41  (3) , 23-34
SNNL: A Programming Language for Spiking Neural Network Development
Spiking Neural Networks (SNNs) are gaining attention for biological plausibility and energy efficiency. Advances in neuromorphic systems—integrating hardware and software tools—accelerate SNN implementation. Yet, deploying SNNs on such platforms remains challenging due to model complexity and system heterogeneity, requiring flexible frameworks. Existing tools (e.g., PyNN, Brian2) show limited expressiveness for neuromorphic applications or poor cross-platform support. This paper proposes SNNL, a flexible domain-specific language for SNN development and deployment on neuromorphic hardware. SNNL decouples neuronal dynamics modeling from network topology specification: equation-based representations handle diverse neuron/synapse models, while hierarchical constructs define complex connectivity patterns. We present a Darwin3-targeted compiler with efficient code generation. Evaluations confirm SNNL achieves precise neuronal dynamic descriptions and flexible network configurations. This work bridges algorithm-hardware gaps in neuromorphic computing by enhancing programmability. Experimental results have demonstrated the feasibility of SNNL in developing SNNs for neuromorphic systems.
- Open Access
- 27 October 2025
- Published by Association for Computing Machinery (ACM)
- p. 499-507
SeMi: When Imbalanced Semi-Supervised Learning Meets Mining Hard Examples
- 27 October 2025
- Published by Association for Computing Machinery (ACM)
- p. 499-507
Open AccessSeMi: When Imbalanced Semi-Supervised Learning Meets Mining Hard Examples
- 24 October 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 75  (1) , 189-203
DepAsync: An Asynchronous SNN Accelerator Based on Core-Dependency
Spiking Neural Networks (SNNs) are widely used in brain-inspired computing and neuroscience research. Several many-core accelerators have been built to improve the running speed and energy efficiency of SNNs. However, current accelerators generally need explicit synchronization among all cores after each timestep of SNNs, which poses a challenge to overall efficiency. This paper proposes DepAsync, an asynchronous architecture that eliminates inter-core synchronization, facilitating fast and energy-efficient SNN inference with commendable scalability. The main idea is to exploit the dependency of neuromorphic cores predetermined at compile time. We design a DepAsync scheduler for each core to trace the running state of its dependencies and control the core to safely forward to the next timestep without waiting for other cores to complete their tasks. This approach prevents the necessity for global synchronization, allowing DepAsync to minimize core waiting time facing inherent core and time imbalance in SNN workloads. The comprehensive evaluations using five SNN workloads show that DepAsync achieves 2.47x speedup and 1.55x energy efficiency compared to the state-of-the-art synchronization architectures.
- 24 October 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 75  (1) , 189-203
DepAsync: An Asynchronous SNN Accelerator Based on Core-Dependency
Spiking Neural Networks (SNNs) are widely used in brain-inspired computing and neuroscience research. Several many-core accelerators have been built to improve the running speed and energy efficiency of SNNs. However, current accelerators generally need explicit synchronization among all cores after each timestep of SNNs, which poses a challenge to overall efficiency. This paper proposes DepAsync, an asynchronous architecture that eliminates inter-core synchronization, facilitating fast and energy-efficient SNN inference with commendable scalability. The main idea is to exploit the dependency of neuromorphic cores predetermined at compile time. We design a DepAsync scheduler for each core to trace the running state of its dependencies and control the core to safely forward to the next timestep without waiting for other cores to complete their tasks. This approach prevents the necessity for global synchronization, allowing DepAsync to minimize core waiting time facing inherent core and time imbalance in SNN workloads. The comprehensive evaluations using five SNN workloads show that DepAsync achieves 2.47x speedup and 1.55x energy efficiency compared to the state-of-the-art synchronization architectures.
- Open Access
- 8 September 2025
- Published by Association for Computing Machinery (ACM)
- p. 258-267
BMapper: A Scalable and Efficient Framework for Brain Simulations Acceleration on Supercomputers
- 8 September 2025
- Published by Association for Computing Machinery (ACM)
- p. 258-267
Open AccessBMapper: A Scalable and Efficient Framework for Brain Simulations Acceleration on Supercomputers
- 24 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Services Computing
- Vol. 18  (5) , 3191-3205
SNN-IoT: Efficient Partitioning and Enabling of Deep Spiking Neural Networks in IoT Services
Spiking Neural Networks (SNNs), due to their inherent biological plausibility and energy-saving characteristics, naturally align with the requirements of IoT services. However, current SNNs require a multi-layer structure to achieve effective applications across various fields. The multi-layer deep SNNs with massive model parameters demand computational resources, rendering them incompatible with resource-constrained IoT devices. To address this problem, in this work, a deep SNN partitioning framework called SNN-IoT is proposed to run complex SNN models on IoT devices. The SNN-IoT first partitions a full deep SNN model into smaller sub-models, leveraging the event-driven sparsity of SNNs and channel-level firing patterns to distribute filters with lower levels of spike activity onto devices with more constrained resources. The SNN model partitioning and deployment is formulated as an optimization problem and is solved using a greedy search assignment mechanism. Furthermore, a channel-wise pruning method exploits the varying degrees of channel activity, effectively reducing each sub-model's size and computational load without compromising performance. Extensive experiments conducted on four non-neuromorphic and two neuromorphic datasets have demonstrated that the SNN-IoT framework not only efficiently partitions deep SNNs and enables their deployment on IoT devices but also significantly reduces the inference latency and energy consumption for IoT services. The experiment uses 9 Raspberry Pi-4B as the IoT devices, and results show that SNN-IoT may reduce the average latency and energy consumption by about 60.7% and 49.9%, respectively, while maintaining the inference accuracy.
- 24 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Services Computing
- Vol. 18  (5) , 3191-3205
SNN-IoT: Efficient Partitioning and Enabling of Deep Spiking Neural Networks in IoT Services
Spiking Neural Networks (SNNs), due to their inherent biological plausibility and energy-saving characteristics, naturally align with the requirements of IoT services. However, current SNNs require a multi-layer structure to achieve effective applications across various fields. The multi-layer deep SNNs with massive model parameters demand computational resources, rendering them incompatible with resource-constrained IoT devices. To address this problem, in this work, a deep SNN partitioning framework called SNN-IoT is proposed to run complex SNN models on IoT devices. The SNN-IoT first partitions a full deep SNN model into smaller sub-models, leveraging the event-driven sparsity of SNNs and channel-level firing patterns to distribute filters with lower levels of spike activity onto devices with more constrained resources. The SNN model partitioning and deployment is formulated as an optimization problem and is solved using a greedy search assignment mechanism. Furthermore, a channel-wise pruning method exploits the varying degrees of channel activity, effectively reducing each sub-model's size and computational load without compromising performance. Extensive experiments conducted on four non-neuromorphic and two neuromorphic datasets have demonstrated that the SNN-IoT framework not only efficiently partitions deep SNNs and enables their deployment on IoT devices but also significantly reduces the inference latency and energy consumption for IoT services. The experiment uses 9 Raspberry Pi-4B as the IoT devices, and results show that SNN-IoT may reduce the average latency and energy consumption by about 60.7% and 49.9%, respectively, while maintaining the inference accuracy.