Kwangwon Lee

The space mission analysis and design process defines a space system at the system level to accomplish space mission objectives. Although the traditional process is well established and comprehensive through several years of experience, we propose a novel design process framework in this paper to aid the traditional process focusing on the following areas of improvement: (1) clarification of the direct connection between mission objectives and final system-level baseline design and requirements, (2) development of a comprehensive quantitative judgment criterion to evaluate various design alternatives, (3) derivation of system drivers and critical requirements after obtaining sufficient design knowledge based on the analysis of big data obtained from exploration of entire design space using an integrated design environment, and (4) system optimization even at the system level with a holistic perspective to guarantee that the baseline design meets the mission objectives. Examples of design steps in the proposed framework are characterizing stakeholder needs and engineering characteristics, building an integrated design environment, exploring and analyzing design space, optimizing system-level design, and elaborating mission utility to ensure an efficient mission-oriented design approach. The proposed framework is implemented in an example space mission involving quantum cryptographic communication. Accordingly, we demonstrate that the proposed framework provides an efficient mission-oriented satellite system-level baseline design.

As microelectronic feature sizes are scaled down, the characteristics and distribution of DRAM data retention time and write recovery time are getting worse. This degradation is due to the increases in the leakage current and resistance of the cell node and the decrease of cell capacitance in DRAM devices. As the physical distance between storage nodes decreases, node potential is increasingly affected by small potential changes in adjacent storage nodes. In this paper, we will show that the one of the most dominant contributors to failure is the adjacent storage node level, and we will demonstrate how node level affects write time delay. The effect of the adjacent storage node level can be correlated with a change in threshold voltage, much like the MOSFET body effect. We define this phenomenon as the lateral body effect, and propose a model for adjacent potential effect using the Buried Cell Array Transistor (BCAT) structure in sub 20nm DRAM.