Naheem Olakunle Adesina

Multiple valued logic (MVL) has proven to be a better alternative and solution to the challenges of traditional binary logic because of its fast computation, fewer interconnects, and small die. It is a potential candidate for future digital design because it allows energy-efficient, low-complex, and high-speed circuits. This paper introduces a new resistive-load two-dimensional field effect transistor-based ternary logic gates, wherein the active resistive-load is replaced with memristor to reduce chip area and power consumption. A memristor-based standard ternary inverter (STI) is designed using GNRFET, MoS2 FET, WSe2 FET, and FinFET, and their performance metric such as delay, power, and energy delay product (EDP) are analyzed. The results show that the proposed design achieves 50% reduction in circuit area, the average power dissipation is reduced by 11.7X, 6.8X, and 3.2X for GNRFET, MoS2 FET, and WSe2 FET, respectively, as compared to FinFET-based ternary inverter. Moreso, other logic gates such as OR, NOR, AND and NAND were simulated in T-SPICE EDA tool, and the results and truth table are in good agreement.

In recent years, graphene has received so much attention because of its superlative properties and its potential to revolutionize electronics, especially in VLSI. This study analyzes the effect of single-event upset (SEU) in an SRAM cell, which employs a metal-oxide semiconductor type graphene nano-ribbon field effect transistor (MOS-GNRFET) and compares the results with another SRAM cell designed using a PTM 10 nm FinFET node. Our simulations show that there is a change in the data stored in the SRAM after a heavy ion strike. However, it recovers from radiation effects after 0.46 ns for GNRFET and 0.51 ns for FinFET. Since the degradation observed in Q and Qb of GNRFET SRAM are 2.7X and 2.16X as compared to PTM nano-MOSFET, we can conclude that GNRFET is less robust to single effect upset. In addition, the stability of SRAM is improved by increasing the supply voltage V_DD.

In recent years, graphene has received so much attention because of its superlative properties and its potential to revolutionize electronics especially in VLSI. This study analyzes the effect of single event upset (SEU) in SRAM cell which employs metal-oxide semiconductor type graphene nano-ribbon field effect transistor (MOS-GNRFET) and compares the results respectively with another SRAM cell designed in PTM 10nm FinFET node. Our simulation show there is a change in data stored in the SRAM after heavy ion strike. However, it recovers from radiation effects after 0.46 ns for GNRFET and 0.51 ns for FinFET. Since the degradation observed in Q and Qb of GNRFET SRAM are 2.7X and 2.16X as compared to PTM nano-MOSFET, we can conclude that GNRFET is less robust to single effect upset. In addition, the stability of SRAM can be improved by increasing the supply voltage VDD.

This work presents the implementation of analytical transport model of MoS ₂ tunnel field effect transistor (TFET) using Verilog-A in Cadence/Spectre. The parameters of the model are extracted, and most notable is its high I _ON /I _OFF ratio, which makes it suitable for low power design, and IoT applications. Subsequently, we employ the TFET model in the design of ultralow power phase locked loop (PLL). Various components of PLL are examined in terms of their structures and functions. The results show that the voltage controlled oscillator (VCO) operates from 0.5 GHz to 2.9 GHz with a tuning range of 82.8%. It also consumes 1.91 μW power at 2 GHz carrier and has a phase noise of -117.3 dBc/Hz at 1 MHz offset frequency. The average power consumed by phase locked loop is 0.021 mW. In addition, the operation of the PLL is not sensitive to temperature variations.

The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.