Fabian Böhm

We propose a “compressed” memory-centric high-order Ising machine (IM) architecture for solving hard optimization problems, featuring guaranteed log-linear hardware area scaling with the number of variables. The key feature of the proposed architecture is a novel unit cell for coupling spins, more complex than comparable IM cells. This unit cell keeps a local copy of a specific spin value, which can be updated when receiving a message of that variable’s change on a common bus. The unit cell also includes circuitry for computing a high-degree product that contributes to the partial derivative of another spin. Because the position of the coupling term in the coupling matrix array is no longer determined by the row and column indices of the constituent spins, we observe up to 75% unit cell utilization in relevant benchmarks. The compressed architecture is especially useful for Boolean satisfiability (SAT) problems, the focus of this study, in that it enables implementation of an “enhanced” Ising machine architecture that preserves clause-variable membership information of the mapped problem. K-SAT problems can be embedded in their native form, allowing such problems to be solved not only by conventional simulated-annealing-based high-order Ising machine dynamics but also with more competitive heuristics inspired by the state-of-the-art SAT solving algorithms. A detailed circuit architecture and design automation methods for mapping SAT problems are presented, and post-layout SPICE simulations are performed. Modeling results for solving random uniform problems show that even the simplest, sequential version of the proposed approach, in which only one spin is flipped at a time, is significantly faster and has comparable energy efficiency while being almost an order of magnitude more compact than previously reported work on combinatorial optimization solvers.

The Boolean satisfiability (SAT) problem is a computationally challenging decision problem central to many industrial applications. For SAT problems in cryptanalysis, circuit design, and telecommunication, solutions can often be found more efficiently by representing them with a combination of exclusive OR (XOR) and conjunctive normal form (CNF) clauses. We propose a hardware accelerator architecture that natively embeds and solves such hybrid XOR–CNF problems using in-memory computing hardware. To achieve this, we introduce an algorithm and demonstrate, both experimentally and through simulations, how it can be efficiently implemented with memristor crossbar arrays. Compared to the conventional approaches that translate XOR–CNF problems to pure CNF problems, our simulations show that the accelerator improves computation speed, energy efficiency, and chip area utilization of in-memory accelerators by ~ 10 × for a set of hard cryptographic benchmarking problems. Moreover, the accelerator achieves a ~ 10 × speedup and a ~ 1000 × gain in energy efficiency over state-of-the-art SAT solvers running on CPUs.

Improving the performance of parallel computing usually comes at the cost of complexity and high energy consumption. This study combines multiple in-memory computing solvers via a parallel-tempering framework, and shows an increase in the speed and energy efficiency of solving binary optimization problems with negligible energy overhead. This approach is expected to have an impact on engineering solutions to Boolean satisfiability problems, Ising machines, and other binary optimization problems with applications in fields such as circuit design and supply-chain management, among others.

The convergence of deep learning and Big Data has spurred significant interest in developing novel hardware that can run large artificial intelligence (AI) workloads more efficiently. Over the last several years, silicon photonics has emerged as a disruptive technology for next-generation accelerators for machine learning (ML). More recently, the heterogeneous integration of III-V compound semiconductors has opened the door to integrating lasers and semiconductor optical amplifiers at wafer-scale, enabling the scaling of the size, density, and complexity of silicon photonic integrated circuits (PICs). Furthermore, using this technology, all of the individual components required to execute the operations within a neural network are available and can be integrated on the same PIC. Here, we review our innovations of an energy-efficient and scalable silicon photonic platform serving as the underlying foundation for next-generation AI accelerator hardware.

Ising machines are a promising non-von-Neumann computational concept for neural network training and combinatorial optimization. However, while various neural networks can be implemented with Ising machines, their inability to perform fast statistical sampling makes them inefficient for training neural networks compared to digital computers. Here, we introduce a universal concept to achieve ultrafast statistical sampling with analog Ising machines by injecting noise. With an opto-electronic Ising machine, we experimentally demonstrate that this can be used for accurate sampling of Boltzmann distributions and for unsupervised training of neural networks, with equal accuracy as software-based training. Through simulations, we find that Ising machines can perform statistical sampling orders-of-magnitudes faster than software-based methods. This enables the use of Ising machines beyond combinatorial optimization and makes them into efficient tools for machine learning and other applications.

Ising machines are a promising non-von-Neumann computational concept for neural network training and combinatorial optimization. However, while various neural networks can be implemented with Ising machines, their inability to perform fast statistical sampling makes them inefficient for training neural networks compared to digital computers. Here, we introduce a universal concept to achieve ultrafast statistical sampling with analog Ising machines by injecting noise. With an opto-electronic Ising machine, we experimentally demonstrate that this can be used for accurate sampling of Boltzmann distributions and for unsupervised training of neural networks, with equal accuracy as software-based training. Through simulations, we find that Ising machines can perform statistical sampling orders-of-magnitudes faster than software-based methods. This enables the use of Ising machines beyond combinatorial optimization and makes them into efficient tools for machine learning and other applications.

Multiple photonic systems show great promise for providing practical yet powerful hardware substrates for neuromorphic computing. Among those, delay-based systems offer -through a time-multiplexing technique - a simple technological implementation route. We discuss our advances in the development of passive coherent fibre-ring cavities and semiconductor lasers with integrated delay for reservoir computing. Time-multiplexed systems are also highly suitable for coherent Ising machines as they allow to implement a fully interconnected large scale system with few components. We have recently proposed a system based on opto-electronic oscillators subjected to self-feedback with improved calculation time and solution quality.

Ising machines based on nonlinear analog systems are a promising method to accelerate computation of NP-hard optimization problems. Yet, their analog nature is also causing amplitude inhomogeneity which can deteriorate the ability to find optimal solutions. Here, we investigate how the system’s nonlinear transfer function can mitigate amplitude inhomogeneity and improve computational performance. By simulating Ising machines with polynomial, periodic, sigmoid and clipped transfer functions and benchmarking them with MaxCut optimization problems, we find the choice of transfer function to have a significant influence on the calculation time and solution quality. For periodic, sigmoid and clipped transfer functions, we report order-of-magnitude improvements in the time-to-solution compared to conventional polynomial models, which we link to the suppression of amplitude inhomogeneity induced by saturation of the transfer function. This provides insights into the suitability of nonlinear systems for building Ising machines and presents an efficient way for overcoming performance limitations.

Various nonlinear systems have been proposed for Ising machines, yet little insight exists into their suitability. We find the choice of nonlinearity to induce order-of-magnitude improvements in time-to-solution for saturable nonlinearities.

Generating and distributing encryption keys via chaos synchronization of optical systems is a promising method for achieving secure and fast real-time encryption of large data volumes. However, current state-of-the-art systems based on lasers subjected to time-delayed feedback have exhibited serious limitations in regard to stability and speed due to their inherent phase sensitivity and their fundamental bandwidth limitation by the laser relaxation oscillation frequency. Here, we propose, simulate, and build a fundamentally different concept based on optoelectronic oscillators (OEOs) to generate and distribute encryption keys. We demonstrate both theoretically and experimentally that by injecting chaotic OEOs with a common external chaotic signal, chaos synchronization can be achieved. The key distribution signal shared between sender and receiver is in the optical domain and can thus be transmitted over a standard fiber-optic network. As the optoelectronic feedback is phase insensitive, stable synchronization becomes possible without any need for active stabilization, resulting in a compact and inexpensive setup. From the chaotic time traces, identical random bit sequences can be generated on the sender’s and receiver’s sides at rates of up to 6 GBit/s, which is comparable to current state-of-the-art systems of the same bandwidth. Since OEOs are not bandwidth limited by relaxation oscillations, the key generation can be further increased compared to laser-based systems by increasing the OEO bandwidth, thus presenting a promising platform for achieving fast and secure real-time encryption.