Zaiming Fu

This paper proposes a high-speed transceiver-based method for implementing a digital-to-time converter (DTC). A real-time decoding technique is introduced to inject time information into high-speed pattern data. The stability of the high-speed clock ensures the high precision of the synthesized timing signal without the need for calibration. The reconfigurability of the clock resources provides the DTC with variable resolution and enhanced flexibility for various applications. Based on this approach, a multifunctional DTC is designed to offer both timing sequence and random timing signal functionalities, catering to a wide range of application scenarios. The timing sequence function generates a continuously variable timing signal stream, while the random timing signal function produces random signals with uniformly distributed time intervals. Experimental results, using a Xilinx Kintex-7 FPGA, validate the effectiveness of the proposed methodology. The system achieves a resolution of 100 ps, a dynamic range from 1 ns to 40 μs, a DNL of -0.02/0.02 LSB, an INL of -0.04/0.03 LSB across the entire range. This approach can be readily adapted to various high-precision timing signal applications.

This paper proposes a new high-resolution digital-to-time converter architecture based on a field programmable gate array and digital-to-analog converter (DAC). A real-time algorithm of time–-amplitude mapping is proposed, which converts the vertical resolution of the DAC to the timing resolution and realizes the ultra-high resolution timing signal generation. Moreover, the relationship between the timing resolution and the vertical resolution and the sampling rate of DAC is discussed. Based on this, arbitrarily distributed random timing signals and editable timing signal sequence functions are realized. This method is verified in the experiment on Xilinx XCKU040 and Texas Instrument DAC37J82. Furthermore, a timing resolution of 1 ps is realized. A time range of 4.2 ns to 999 s, an editable sequence length of 1–128k, and excellent nonlinear performance are achieved. In addition, functions for arbitrarily distributed random timing signals and signal bursts are tested. This method can be flexibly deployed on existing hardware and satisfy almost all test requirements.

In the design of SDRAM-based arbitrary waveform generators, the conflict between the randomness of dynamic memory output data flow and the requirement of seamless signal output is a non-negligible problem, especially in generators with hopping functions and high sampling rates. By imposing appropriate constraints in the design, the continuity of the output signal and the high throughput utilization can be guaranteed, and the constraints can be modeled to obtain the design boundary requirements under different specifications. In this paper, we analyze the throughput model of SDRAM and the access characteristics of an arbitrary waveform generator with jump capability. We establish a minimum waveform segment length model and a buffer size model to guarantee continuous signal output, which can obtain sufficient conditions for seamless synthesis of arbitrary waveform generators and be used to support the repeat/jump function of multi-segment waveforms. Experimental results on a DDR3 SDRAM-based generator show that the minimum waveform segment length obtained is within 11 words of the measured boundary, and the minimum buffer size is within 10 words of the measured boundary, which can effectively improve hardware resource utilization.

A pulse signal generator is an essential tool in electronic testing, which can generate pulse signals with adjustable amplitude, frequency, edge time, and pulse width. Ultra-low duty cycle pulse signals have extremely narrow pulse widths and usually have swift edge times, making them have ultra-wideband signals' characteristics. Such a situation undoubtedly puts higher requirements on the performance indicators of electronic measurement systems. Many existing integrated circuit processes limit the current electronic system and cannot condition and synthesize ultra-low duty cycle pulse signals. In this paper, we propose a pulse signal synthesis method based on the sub-band decomposition of pulse waveform to address the problem that the performance of devices in the signal conditioning channel cannot meet the conditioning of high-speed pulse signals, which effectively reduces the required bandwidth of the pulse waveform for electronic devices, fills the deficiency of the waveform conditioning system in the ultra-wide bandwidth problem, and minimizes the attenuation of the waveform frequency components. It has been shown experimentally that the pulse signal synthesis scheme based on sub-band decomposition is highly accurate.

The development of digital technology has driven the progress of the digital field. As a result, the development and testing of these complex digital systems require integrated test equipment with various functions to perform various stages of testing to ensure the effectiveness and accuracy of the system. The digital test signal plays an indispensable role in the testing process of digital systems. It is widely used as a test excitation source in the field of time-domain measurements such as integrated circuit testing, bus testing, and electronic measure-ments. However, traditional digital test signal generators are pretty bulky and limited in terms of test signal options and functions. This makes them inadequate for handling complex test scenarios. In order to tackle the problems mentioned above, this paper proposes a new architecture of a fully adjustable multi-functional digital test signal generator based on Field-Programmable Gate Arrays (FPGA). This design approach reduces the use of hardware resources as well as integrates multiple digital test signal generation. Based on the proposed new design methodology, we have implemented a 16-channel digital test signal generator. The generator is capable of simulating a variety of digital test signal generation, and the 16 output channels can be independently controlled. Output digital test signal data rate is 1 kbit/s to 100 Mbit/s, adjustable resolution is 1 kbit/s. Customizable editing length 16 kbit/CH. Output signal supports voltage conditioning, output level range -1 V to +5 V, resolution 10 mV. And the rise time and fall time of the output signal can be adjusted.

This paper presents a design for a multi-level pattern generator based on Field Programmable Gate Array (FPGA) and Digital to Analog Converter (DAC). The proposed generator utilizes dynamic time error control to synthesize multi-level and pseudo-random bit sequence (PRBS) coding patterns, thereby expanding the application range of the pattern generator. To overcome the limited speed of FPGA logic resources and achieve a sample rate of 1.25 giga samples per second (GSPS) for the DAC, the design incorporates eight parallel channels of a processing unit. Experimental results demonstrate that the pattern generator can synthesize pattern signals at rates up to 120 mega samples per second (MBd) with voltage magnitudes of 2-level, 3-level, and 4-level.

In this paper, a novel ultra-high timing resolution pulse generator is proposed. It is based on the waveform real-time computation method. Through real-time computing and filtering of the waveform samples, a pulse with a 0.1 ps timing resolution pulse could be generated at a 2.5 GSPS sampling rate. Based on the waveform real-time computation method, jitters are injected into the waveform time parameter to break the harmonic components caused by non-integer multiples of the sampling rate and waveform frequency. Waveform spurs are further suppressed using this approach. The pulse error correction is achieved by designing digital filters that complement the waveform distortion features. The complementary digital filters are then combined as Farrow filter coefficients by polynomial fitting. Based on the real-time computation method, pulse width modulation, frequency modulation, and amplitude modulation are easy to realize. The implemented pulse generator has four channels, whose minimum pulse width, edge time, frequency range, and amplitude range are 4, 2.5 ns, 1 μHz–120 MHz, and 50 mVpp–5 Vpp, respectively. All timing resolution and timing accuracy of pulse width, edge time, pulse period, and channel delay are 0.1 and 50 ps, respectively. Timing parameters can be changed continuously without glitches.

Jitter is one of the main factors affecting the bit error rate, and jitter decomposition is a crucial tool with which to characterize jitter at a given BER. In this article, we address this problem based on PointNet and propose a PointNet-based dual-Dirac model (PointNet-DD), where its input is the two-dimensional point cloud formed by the coordinate of the jitter histogram. In particular, we develop a feature extractor, where the stride size of the one-dimensional convolution layer of PointNet is changed to better learn the local features, the corresponding variance and mean features hidden under the jitter histogram point cloud are extracted by global max pooling and global average pooling, respectively. Then, we introduce a dual-Dirac model in the network for jitter calculation to make the estimated deterministic jitter and random jitter more accurate. Consequently, the PointNet-DD can improve the mean absolute error of jitter decomposition. Finally, this approach is practically tested on the test circuits. Experimental results show that the performance, robustness, space, and time of the proposed method are better than other methods.