Kanad Basu

Hardware verification is crucial in modern SoC design, consuming around 70% of development time. SystemVerilog assertions ensure correct functionality. However, existing industrial practices rely on manual efforts for assertion generation, which becomes increasingly untenable as hardware systems become complex. Recent research shows that Large Language Models (LLMs) can automate this process. However, proprietary SOTA models like GPT-4o often generate inaccurate assertions and require expensive licenses, while smaller open-source LLMs need fine-tuning to manage HDL code complexities. To address these issues, we introduce VERT, an open-source dataset designed to enhance SystemVerilog assertion generation using LLMs. VERT enables researchers in academia and industry to fine-tune open-source models, outperforming larger proprietary ones in both accuracy and efficiency while ensuring data privacy through local fine-tuning and eliminating costly licenses. The dataset is curated by systematically augmenting variables from open-source HDL repositories to generate synthetic code snippets paired with corresponding assertions. Experimental results demonstrate that fine-tuned models like Deepseek Coder 6.7B and Llama 3.1 8B outperform GPT-4o, achieving up to 96.88% improvement over base models and 24.14% over GPT-4o on platforms including OpenTitan, CVA6, OpenPiton, and Pulpissimo. VERT is available at https://github.com/AnandMenon12/VERT .

The widespread adoption of deep neural network (DNN)-based learning systems in safety-critical applications requires exceptional reliability. However, this reliability could be compromised by perturbations in model parameters, such as variations in neural network weights caused by hardware vulnerabilities and environmental factors, which can lead to mispredictions and compromise system safety. To address this, we propose ‘ModelStar’, an innovative framework leveraging reachability analysis to evaluate the robustness of DNNs against weight perturbations. ModelStar employs a linear set propagation technique to analyze the impact of an infinite family of parameter variations on DNN outputs. Our comprehensive analysis demonstrates that ModelStar not only establishes tighter robustness bounds but also verifies DNN robustness for up to 60% more samples from image classification datasets compared to existing methods. Furthermore, ModelStar extends safety verification to convolutional layers, advancing the state-of-the-art in neural network safety verification. These results highlight ModelStar’s efficacy in improving the reliability of DNNs in real-world, safety-critical scenarios.

Power side-channel (PSC) attacks exploit power consumption patterns to extract sensitive information, posing risks to cryptographic operations crucial for secure systems. Traditional countermeasures, such as masking, face challenges like complex synthesis integration, high area overhead, and vulnerability to optimization removal during logic synthesis. To address these issues, we introduce proposed side-channel aware synthesis (PoSyn), a novel logic synthesis framework designed to enhance cryptographic hardware’s resistance against PSC attacks. Our approach focuses on the optimal bipartite mapping of vulnerable register transfer level (RTL) components to standard cells from the technology library to minimize PSC leakage. By employing a cost function that integrates key characteristics from the RTL design and the standard cell library, we strategically modify the mapping criteria during the conversion of RTL designs into standard cell netlists without altering the design functionality. Furthermore, PoSyn is theoretically shown to minimize mutual information leakage, further reinforcing its security against PSC vulnerabilities. PoSyn is evaluated on a variety of cryptographic hardware, including AES, RSA, PRESENT, and postquantum cryptography algorithms like Saber and CRYSTALS-Kyber across 65-, 45-, and 15-nm nodes. Our experimental results demonstrate a significant reduction of success rates for differential power analysis (DPA) and correlation power analysis (CPA) attacks, as low as 3% and 6%, respectively. Furthermore, test vector leakage assessment (TVLA) confirms that the synthesized netlists exhibit negligible leakage. Moreover, compared to traditional countermeasures such as masking and shuffling, PoSyn achieves notably lowers the success rates, achieving a reduction by up to 72%, while simultaneously enhancing area efficiency by as much as $3.79\times $ . These results highlight the effectiveness of PoSyn in securing cryptographic hardware with minimal impact on area and performance.

Edge AI accelerators, such as TPUs, NPUs, and custom low-power ASICs—are increasingly used in real-time, battery-operated systems for on-device deep learning. However, their deployment in resource-constrained and physically exposed environments raises serious concerns about hardware reliability and security. Faults in these systems can be transient (e.g., due to voltage fluctuations or radiation), permanent (e.g., aging or manufacturing defects), or even adversarially induced through targeted bit-flip attacks. This survey provides a comprehensive overview of hardware faults in AI accelerators, with a particular focus on edge deployment scenarios.We examine the fault models, detection and mitigation techniques, and unique challenges posed by limited on-chip resources and real-time constraints. Unlike prior surveys focusing mainly on random fault tolerance in general-purpose settings, our work highlights how faults at the edge can also be intentional attack vectors, blurring the line between reliability and security. The goal is to guide the development of resilient edge AI hardware capable of withstanding natural and malicious fault events.

Efficient adaptation of large language models (LLMs) on edge devices is crucial for applications that need ongoing, privacy-preserving adaptation and inference. This is particularly crucial for mission-critical applications, such as drones, where hardware resources are limited, and the system’s overall security must operate within a zero-trust environment. In order to address these challenges, we propose a novel low-overhead hardware architecture that enables secure LLM operations on the edge. Furthermore, the proposed scheme incorporates a secure communication framework to maintain the integrity of edge operations against an external zero-trust network environment. If successful, this project will lay the foundation for a low-overhead edge environment to execute LLMs while maintaining the privacy and integrity of the system.